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SCNN: An accelerator for compressed-sparse convolutional neural networks
International Symposium on Computer Architecture, 2017Convolutional Neural Networks (CNNs) have emerged as a fundamental technology for machine learning. High performance and extreme energy efficiency are critical for deployments of CNNs, especially in mobile platforms such as autonomous vehicles, cameras ...
Angshuman Parashar +8 more
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Timeloop: A Systematic Approach to DNN Accelerator Evaluation
IEEE International Symposium on Performance Analysis of Systems and Software, 2019This paper presents Timeloop, an infrastructure for evaluating and exploring the architecture design space of deep neural network (DNN) accelerators. Timeloop uses a concise and unified representation of the key architecture and implementation attributes
Angshuman Parashar +9 more
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ViA: A Novel Vision-Transformer Accelerator Based on FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022Since Google proposed Transformer in 2017, it has made significant natural language processing (NLP) development. However, the increasing cost is a large amount of calculation and parameters.
Teng Wang +6 more
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A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm
IEEE Journal of Solid-State Circuits, 2023The energy efficiency of deep neural network (DNN) inference can be improved with custom accelerators. DNN inference accelerators often employ specialized hardware techniques to improve energy efficiency, but many of these techniques result in ...
Ben Keller +8 more
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Accelerated entropy estimates with accelerated dynamics
The Journal of Chemical Physics, 2007Accelerated dynamics is applied to entropy calculations on a set of toy and molecular systems and is found to enhance the rate of convergence.
David D L, Minh +2 more
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PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference
International Conference on Architectural Support for Programming Languages and Operating Systems, 2019Memristor crossbars are circuits capable of performing analog matrix-vector multiplications, overcoming the fundamental energy efficiency limitations of digital logic. They have been shown to be effective in special-purpose accelerators for a limited set
Aayush Ankit +10 more
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To accelerate or not to accelerate? That is the question
The Physics Teacher, 2010Thanks to Jim Hicks, Barrington High School, and Jaime Stasiorowski and Kristen Piggott, Deerfield High School, for their help with this month's column. If you have a YouTube video you use in class, please send the link and a brief description to: driendeau@dist113.org.
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MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product
Micro, 2020Sparse-sparse matrix multiplication (SpGEMM) is a computation kernel widely used in numerous application domains such as data analytics, graph processing, and scientific computing.
Nitish Srivastava +4 more
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Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology
Micro, 2017Many important applications trigger bulk bitwise operations, i.e., bitwise operations on large bit vectors. In fact, recent works design techniques that exploit fast bulk bitwise operations to accelerate databases (bitmap indices, BitWeaving) and web ...
Vivek Seshadri +9 more
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