Results 111 to 120 of about 52,583 (159)

CMOS Characterization and Compact Modelling for Circuit Reliability Simulation

IEEE International Symposium on On-Line Testing and Robust System Design, 2018
With nowadays nanometer-CMOS technologies, time-zero and time dependent variability effects (like BTI, CHI, RTN, TDDB, EM, etc) have turned into an even more serious threat to the desired performance of analog and digital integrated circuits. Statistical
J. Diaz-Fortuny, J. Martín-Martínez, R. Rodríguez, M. Nafría, R. Castro-López, E. Roca, F. Fernández   +6 more
semanticscholar   +1 more source

Snubber and Metal Oxide Varistor Optimization Design of Modular IGCT Switch for Overvoltage Suppression in Hybrid DC Circuit Breaker

IEEE Journal of Emerging and Selected Topics in Power Electronics, 2021
The power electronic switches have great influences on the performance of the hybrid dc circuit breaker (DCCB). Recently, the integrated gate commutated thyristor (IGCT) is considered to be a suitable alternative full-control power device due to its high
Q. Yi, Fei Yang, Yife Wu, Yi Wu, C. Gao, W. Zhuang, M. Rong   +6 more
semanticscholar   +1 more source

Multiexpression Symbolic Regression and Its Circuit Design Case

IEEE Transactions on Systems, Man, and Cybernetics: Systems
Symbolic regression is commonly considered in wide-ranging applications due to its inherent capability for learning both structure and weighting parameters of an interpretable model. However, for those scenarios that require fitting multiple expressions (
Yu Zhang, Xinyue Li, Wang Hu, Gary G. Yen   +3 more
semanticscholar   +1 more source

Development of AI-Based Simulation Circuit Design and Assistance Systems

2024 IEEE 6th International Conference on Civil Aviation Safety and Information Technology (ICCASIT)
Artificial intelligence (AI) algorithms have vast application prospects in the field of analog circuit design. This paper introduces an AI algorithm-based assisted system for analog circuit design.
Shaohang Cao
semanticscholar   +1 more source

Design of a Current Mode Multiplexed Circuit for Integrate & Fire Neuromorphic Systems

IEEE Nordic Circuits and Systems Conference, 2020
The design of a multi-chip architecture can be an effective solution to implement very large Artificial Neural Networks systems. Undoubtedly, the size of these systems often represents an arduous obstacle in the way of a deep and effective investigation ...
V. Bonaiuto, F. Sargeni
semanticscholar   +1 more source

Modeling of Thermal Coupling and Temperature Sensor Circuit Design Considerations for Hardware Trojan Detection

Midwest Symposium on Circuits and Systems, 2018
This paper describes the development of a model for the simulation of electrothermal coupling to detect malicious circuits with on-chip temperature sensors.
Mengting Yan, Haoran Wei, M. Onabajo
semanticscholar   +1 more source

EEsizer: LLM-Based AI Agent for Sizing of Analog and Mixed Signal Circuit

IEEE Transactions on Circuits and Systems Part 1: Regular Papers
The design of Analog and Mixed-Signal (AMS) integrated circuits (ICs) often involves significant manual effort, especially during the transistor sizing process. While Machine Learning techniques in Electronic Design Automation (EDA) have shown promise in
Chang Liu, D. Chitnis
semanticscholar   +1 more source

MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs

2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
The emergence of multimodal large language models (MLLMs) presents promising opportunities for automation and enhancement in Electronic Design Automation (EDA). However, comprehensively evaluating these models in circuit design remains challenging due to
Chenchen Zhao, Zheng-Hao Shi, Xiangyu Wen, Chengjie Liu, Yi Liu, Yunhao Zhou, Yuxiang Zhao, Hefei Feng, Yinan Zhu, Gwok-Waa Wan, Xin Cheng, Weiyu Chen, Yongqing Fu, Chujie Chen, Chenhao Xue, Guangyu Sun, Ying Wang, Yibo Lin, Jun Yang, Ning Xu, Xi Wang, Qiang Xu   +21 more
semanticscholar   +1 more source

SRAM Periphery Testing Using the Cell-Aware Test Methodology

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing memory circuits is crucial for ensuring the quality and reliability of system-on-chip (SoC) designs, especially as shrinking technology nodes increase susceptibility to nanometer-scale defects.
Xhesila Xhafa, Eric Faehn, Patrick Girard, Arnaud Virazel   +3 more
semanticscholar   +1 more source

AnaCraft: Duel-Play Probabilistic-Model-Based Reinforcement Learning for Sample-Efficient PVT-Robust Analog Circuit Sizing Optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Recent advancements in machine learning offer the potential for finding faster and robust optimization approaches for analog circuit design automation. However, fully automated yet fast and process, voltage, and temperature (PVT)-robust sizing algorithms
Mohsen Ahmadzadeh, J. Lappas, Norbert Wehn, Georges G. E. Gielen   +3 more
semanticscholar   +1 more source