Results 61 to 70 of about 9,756 (260)

Stochastic pulse coded arithmetic

2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000
Among the different pulse codification techniques, stochastic pulse codification has its own arithmetic based on the similarity between Boolean algebra and statistical algebra. Summation and multiplication are the two basic arithmetic operations treated in depth in the literature.
Toral, S. L., Quero Reboul, José Manuel, García Franquelo, Leopoldo   +2 more
openaire   +3 more sources

Targeting CXCR2 in Nociceptive Sensory Neurons Offers Novel Therapeutic Potentials for Postoperative Pain

Advanced Science, EarlyView.
Tissue incision induces CXCL5 release, which activates neuronal CXCR2 on incision‐innervating sensory neurons. Neuronal CXCR2 couples with TRPA1 to drive mechanical pain and engages p38 MAPK signaling to upregulate TRPV1 and promote heat pain. Targeted Cxcr2 knockdown relieves incisional pain while preserving CXCR2‐dependent neutrophil responses ...
Yushuang Pan, Peiyi Li, Yufeng Chen, Zishan Dong, Yuanyuan Li, Boyu Liu, Yan Tai, Chuan Wang, Jianqiao Fang, Chengyu Yin, Boyi Liu   +10 more
wiley   +1 more source

Coarsely Quantized Decoding and Construction of Polar Codes Using the Information Bottleneck Method

Algorithms, 2019
The information bottleneck method is a generic clustering framework from the field of machine learning which allows compressing an observed quantity while retaining as much of the mutual information it shares with the quantity of primary relevance as ...
Syed Aizaz Ali Shah, Maximilian Stark, Gerhard Bauch   +2 more
doaj   +1 more source

Learning Work Function via Implicit Reasoning on Electrostatic Potential Landscapes

Advanced Science, EarlyView.
StructPot‐CLR establishes a cross‐modal contrastive learning framework that aligns the crystal structures of 2D materials with plane‐averaged electrostatic potential landscapes for physically informed work‐function prediction. The model achieves an MAE of 0.265 eV and an R2 of 0.902 on the held‐out test set while accurately preserving key morphological
Haoyu Wan, Yue Wu, Tianhao Su, Deng Pan
wiley   +1 more source

SigmaFormer: Augmenting transformer encoders with COSMO sigma profiles for pure component property prediction

AIChE Journal, EarlyView.
Abstract Transformer‐based molecular models pretrained on SMILES strings demonstrate strong performance in property prediction. However, these model often lack explicit integration of molecular surface charge distributions that govern intermolecular interactions such as hydrogen bonding and polarity.
Tae Hyun Kim, Silabrata Pahari, Joseph Sang‐Il Kwon   +2 more
wiley   +1 more source

Hardware acceleration of number theoretic transform for zk‐SNARK

Engineering Reports, EarlyView., 2023
An FPGA‐based hardware accelerator with a multi‐level pipeline is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. It can be flexibly scaled to different scales of FPGAs and has been equipped in the heterogeneous acceleration system with the help of HLS and OpenCL.
Haixu Zhao, Dong Ding, Feng Wang, Pengcheng Hua, Ning Wang, Qin Wu, Zhilei Chai   +6 more
wiley   +1 more source

Adaptive Frequency and Assignment Algorithm for Context-Based Arithmetic Compression Codes for H.264 Video Intraframe Encoding

Engineering Proceedings
In modern communication technology, short videos are increasingly used on social media platforms. The advancement of video codecs is pivotal in communication. In this study, we developed a new scheme to encode the residue of intraframes.
Huang-Chun Hsu, Jian-Jiun Ding
doaj   +1 more source

Overlapped Arithmetic Codes

CoRR
Arithmetic codes are usually deemed as the most important means to implement lossless source coding, whose principle is mapping every source symbol to a sub-interval in [0, 1). For every source symbol, the length of its mapping sub-interval is exactly equal to its probability.
openaire   +2 more sources

A Memristor‐Based In‐Memory Computing System‐on‐Chip with Efficient Depthwise Convolution

Advanced Intelligent Systems, EarlyView.
We present a memristor‐based in‐memory computing (IMC) architecture that enables efficient depthwise convolution (DWC) acceleration. Fabricated in a system‐on‐chip with crossbar arrays, the design improves memory utilization. Experimental validation demonstrates the first hardware acceleration of DWC in IMC, achieving a digital comparable inference ...
Wenhao Song, Fuxi Cai, Sangsu Park, Zhaoyan Li, Seonghun Lee, Mingyi Rao, Woohyung Choi, Seungin Shin, Yan Zhu, Sujin Chae, Myoungsub Kim, Mingche Wu, Hyejung Choi, Yuan Dao, Jaeyun Yi, Youngman Cho, Seon Yong Cha, Ning Ge, Qiangfei Xia, Soo Gil Kim, Miao Hu, J. Joshua Yang   +21 more
wiley   +1 more source

Exploiting Ferroelectric and Spintronic Dynamics for Neural Network Computation

Advanced Intelligent Systems, EarlyView.
Ferroelectric and spintronic devices, relying on the control of polarization and magnetization, offer intrinsically fast, durable, energy‐efficient, and low‐latency building blocks for analog in‐memory computing. The hysteretic dynamics of an order parameter are leveraged to provide nonvolatile, multistate memory and nonlinear switching. Brain‐inspired
Dashiell Harrison, Kevin Nadaud, Josquin Harrison, Guillaume F. Nataf, Laura Bégon‐Lours   +4 more
wiley   +1 more source