Results 201 to 210 of about 1,831,585 (228)
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Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95, 1995
This paper describes a new Asynchronous, Parallel, Event Driven Simulation algorithm with inconsistent event Preemption, P/sup 2/EDAS. P/sup 2/EDAS represents a significant advancement in distributed conservative digital circuit simulation algorithms in that it permits the use of any number of non-zero propagation delays for every path between the ...
Peter A. Walker, Sumit Ghosh
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This paper describes a new Asynchronous, Parallel, Event Driven Simulation algorithm with inconsistent event Preemption, P/sup 2/EDAS. P/sup 2/EDAS represents a significant advancement in distributed conservative digital circuit simulation algorithms in that it permits the use of any number of non-zero propagation delays for every path between the ...
Peter A. Walker, Sumit Ghosh
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The parallel execution of DO loops
Communications of the ACM, 1974 Methods are developed for the parallel execution of different iterations of a DO loop. Both asynchronous multiprocessor computers and array computers are considered. Practical application to the design of compilers for such computers is discussed.
Leslie Lamport
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Highly efficient asynchronous execution of large-grained parallel programs
Proceedings of 1993 IEEE 34th Annual Foundations of Computer Science, 2002An n-thread parallel program p is large-grained if in every parallel step the computations on each of the threads are complex procedures requiring numerous processor instructions. This practically relevant style of programs differs from PRAM programs in its large granularity and the possibility that within a parallel step the computations on different ...
Yonatan Aumann +3 more
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A Transfer-Aware Runtime System for Heterogeneous Asynchronous Parallel Execution
ACM SIGARCH Computer Architecture News, 2016This paper presents a novel resource management approach for efficiently managing the computation and the data movements between the host and its accelerators in a heterogeneous platform. Our approach is based on OmpSs, with support for multi-core CPUs, GPGPUs and Maxeler Data Flow Engines based on FPGA technology; it exploits data locality, data ...
Soukaina N. Hmid +2 more
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Analysis of Asynchronous Execution Streams with I-Caching in Massively Parallel Systems
Journal of Parallel and Distributed Computing, 1993Abstract Real world parallel systems on a massive scale have been limited to SIMD architectures due to the prohibitive cost of multiple instruction memories. Although many of these systems could benefit from an asynchronous MIMD control structure, it is unlikely that every processing element will execute a different set of instructions.
Serge M. Manning, David G. Meyer
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Proceedings of the VLDB Endowment, 2015
The bulk synchronous parallel (BSP) model used by synchronous graph processing systems allows algorithms to be easily implemented and reasoned about. However, BSP can suffer from poor performance due to stale messages and frequent global synchronization barriers.
Minyang Han, Khuzaima Daudjee
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The bulk synchronous parallel (BSP) model used by synchronous graph processing systems allows algorithms to be easily implemented and reasoned about. However, BSP can suffer from poor performance due to stale messages and frequent global synchronization barriers.
Minyang Han, Khuzaima Daudjee
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IEEE Transactions on Computers, 2001
The DoD's very high speed integrated circuit Hardware Description Language, VHDL, is aimed at allowing hardware designers to accurately describe, simulate, and validate combinational and sequential hardware designs on computers prior to building a prototype.
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The DoD's very high speed integrated circuit Hardware Description Language, VHDL, is aimed at allowing hardware designers to accurately describe, simulate, and validate combinational and sequential hardware designs on computers prior to building a prototype.
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AESPA: Asynchronous Execution Scheme to Exploit Bank-Level Parallelism of Processing-in-Memory
56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023Hongju Kal, Chanyoung Yoo, Won Woo Ro
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mpi4py.futures: MPI-Based Asynchronous Task Execution for Python
IEEE Transactions on Parallel and Distributed Systems, 2023Lisandro Dalcin, David Elliot Keyes
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