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Bitwise MSB Radix Sort on AVX-512
, 2021 Möller R.
Möller, Ralf ; https://orcid.org/
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Impact of AVX-512 Instructions on Graph Partitioning Problems.
50th International Conference on Parallel Processing Workshop, 2021Graph analysis now percolates society with applications ranging from advertising and transportation to medical research. The structure of graphs is becoming more complex every day while they are getting larger. The increasing size of graph networks has made many of the classical algorithms reasonably slow. Fortunately, CPU architectures have evolved to
Md. Maruf Hossain, Erik Saule
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AVX-512 Based, High-Throughput LDPC Decoders
2021 6th International Conference on Image, Vision and Computing (ICIVC), 2021Low Density Parity Check (LDPC) codes can approach the Shannon limit in digital communication systems and have good error correction performance. At present, with the continuous development of communication technology, the demand for the throughput of the communication system is also increasing.
Jingxin Dai +3 more
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Using Advanced Vector Extensions AVX-512 for MPI Reductions
27th European MPI Users' Group Meeting, 2020As the scale of high-performance computing (HPC) systems continues to grow, researchers are devoted themselves to explore increasing levels of parallelism to achieve optimal performance. The modern CPU’s design, including its features of hierarchical memory and SIMD/vectorization capability, governs algorithms’ efficiency.
Dong Zhong +3 more
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AVX-512 Based Software Decoding for 5G LDPC Codes
2019 IEEE International Workshop on Signal Processing Systems (SiPS), 2019In this paper, we investigate how the 5G NR LDPC codes can be decoded by GPP effectively with single instruction-multiple-data (SIMD) acceleration and evaluate the corresponding achievable throughput on newly released Intel Xeon CPUs. Firstly, a general software implementation architecture with SIMD acceleration for horizontal-layered LDPC decoding is ...
Yi Xu +3 more
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Enhanced Vector Math Support on the Intel®AVX-512 Architecture
2018 IEEE 25th Symposium on Computer Arithmetic (ARITH), 2018The Intel®AVX-512 architecture adds new capabilities such as masked execution, floating-point exception suppression and static rounding modes, as well as a small set of new instructions for mathematical library support. These new features allow for better compliance with floating-point or language standards (e.g.
Cristina S. Anderson +2 more
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AVX-512 Programming – Floating-Point
2018In previous chapters, you learned how to carry out scalar and packed floating-point operations using the AVX and AVX2 instruction sets. In this chapter, you learn how to perform these operations using the AVX-512 instruction set. The first part of this chapter contains source code examples that illustrate basic AVX-512 programming concepts using scalar
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AVX-512 Programming – Packed Integers
2018In the previous chapter, you learned how to use the AVX instruction set to perform calculations using packed floating-point operands. In this chapter, you learn how to carry out computations using packed integer operands. Similar to the previous chapter, the first few source code examples in this chapter demonstrate basic arithmetic operations using ...
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