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Contention-Aware Dynamic Memory Bandwidth Isolation with Predictability in COTS Multicores: An Avionics Case Study [PDF]

Euromicro Conference on Real-Time Systems, 2017
Airbus is investigating COTS multicore platforms for safety-critical avionics applications, pursuing helicopter-style autonomous and electric aircraft. These aircraft need to be ultra-lightweight for future mobility in the urban city landscape. As a step
Ankit Agrawal, G. Fohler, Johannes Freitag, Jan Nowotsch, S. Uhrig, M. Paulitsch   +5 more
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MTFT: Multi-Tenant Fair Throttling

International Conference on Big Data and Smart Computing, 2023
Distributing resources fairly to tenants is important in cloud data center. However, traditional Fair I/O schedulers are not suitable for container environments. It is because of the unfairness and performance degradations.
Il-Bing Song, Sang-Won Lee
semanticscholar   +1 more source

Instruction Profiling Based Predictive Throttling for Power and Performance

IEEE transactions on computers, 2023
Technology scaling has long been the driving force for reducing power consumption in microprocessor design. As scaling has reached its limits, new techniques are being adopted to address the power problem.
A. Owahid, E. John
semanticscholar   +1 more source

MemPol: Policing Core Memory Bandwidth from Outside of the Cores

IEEE Real Time Technology and Applications Symposium, 2023
In today’s multiprocessor systems-on-a-chip (MP- SoC), the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worstcase execution ...
Alexander Zuepke, Andrea Bastoni, Weifan Chen, M. Caccamo, R. Mancuso   +4 more
semanticscholar   +1 more source

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling

IEEE Journal of Solid-State Circuits, 2022
Reduced precision computation is a key enabling factor for energy-efficient acceleration of deep learning (DL) applications. This article presents a 7-nm four-core mixed-precision artificial intelligence (AI) chip that supports four compute precisions ...
Sae Kyu Lee, A. Agrawal, J. Silberman, M. Ziegler, Mingu Kang, Swagath Venkataramani, N. Cao, Bruce M. Fleischer, Michael Guillorn, Matthew Cohen, S. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, S. Koswatta, Ching Zhou, V. Zalani, Monodeep Kar, J. Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, A. Herbert, Radhika Jain, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, M. Schaal, Kerstin Schelm, M. Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wen Wang, Xin Zhang, Vinay Shah, B. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, K. Gopalakrishnan, Le Chang   +43 more
semanticscholar   +1 more source

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling

IEEE International Solid-State Circuits Conference, 2021
Low-precision computation is the key enabling factor to achieve high compute densities (T0PS/W and T0PS/mm2) in AI hardware accelerators across cloud and edge platforms.
A. Agrawal, Sae Kyu Lee, J. Silberman, M. Ziegler, Mingu Kang, Swagath Venkataramani, N. Cao, Bruce M. Fleischer, Michael Guillorn, Matthew Cohen, S. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, S. Koswatta, Ching Zhou, V. Zalani, J. Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, A. Herbert, Radhika Jain, Monodeep Kar, Kyu-Hyoun Kim, Yulong Li, Z. Ren, Scot Rider, M. Schaal, Kerstin Schelm, M. Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, B. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Leland Chang, K. Gopalakrishnan   +43 more
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Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs

Design Automation Conference, 2023
Embedded systems are increasingly adopting heterogeneous templates integrating hardware accelerators and application-specific processors, which poses novel challenges.
Gianluca Brilli, Giacomo Valente, Alessandro Capotondi, P. Burgio, T. D. Masciov, Paolo Valente, A. Marongiu   +6 more
semanticscholar   +1 more source

Glint: Decentralized Federated Graph Learning with Traffic Throttling and Flow Scheduling

International Workshop on Quality of Service, 2021
Federated learning has been proposed as a promising distributed machine learning paradigm with strong privacy protection on training data. Existing work mainly focuses on training convolutional neural network (CNN) models good at learning on image/voice ...
Tao Liu, Pengjie Li, Yu-Lei Gu
semanticscholar   +1 more source

LIBRA: Clearing the Cloud Through Dynamic Memory Bandwidth Management

International Symposium on High-Performance Computer Architecture, 2021
Modern Cloud Service Providers (CSP) heavily co-schedule tasks with different priorities on the same computing node to increase server utilization. To ensure the performance of high priority jobs, CSPs usually employ Quality-of-Service (QoS) mechanisms ...
Ying Zhang, Jian Chen, Xiaowei Jiang, Qiang Liu, I. Steiner, Andrew J. Herdrich, Kevin Shu, Ripan Das, Longhai Cui, Litrin Jiang   +9 more
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Test Time Reduction with Data Throttling Techniques in a Multi Core SoC Design

International Symposium on VLSI Design and Test
Test time and test volume reduction have been a serious concern in 7nm or lower technology nodes. In the era of AI, SoC sizes and number of cores used in the SoC ensures Moore’s law in the Semiconductor industry for the unforeseeable future. There are no
Jatin Chakravarti, Chintan Panchal
semanticscholar   +1 more source