Results 131 to 140 of about 589,245 (147)

Factors Affecting the Accuracy of Operation of the Electrohydraulic Actuation Position System With Throttling Control

Conference proceedings
The paper analyses most of the factors that influence the positioning error in the stationary mode of the electrohydraulic positional actuation systems and several ways to calculate the positioning accuracy in relation to the considered factors that ...
Dragan B. Nauparac, N. Visnjic
semanticscholar   +1 more source

Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-Based Heterogeneous SoCs

IEEE Transactions on Parallel and Distributed Systems
Commercial embedded systems increasingly rely on heterogeneous architectures that integrate general-purpose, multi-core processors, and various hardware accelerators on the same chip.
Giacomo Valente, Gianluca Brilli, T. D. Mascio, Alessandro Capotondi, P. Burgio, Paolo Valente, A. Marongiu   +6 more
semanticscholar   +1 more source

Test Time Reduction with Data Throttling Techniques in a Multi Core SoC Design

International Symposium on VLSI Design and Test
Test time and test volume reduction have been a serious concern in 7nm or lower technology nodes. In the era of AI, SoC sizes and number of cores used in the SoC ensures Moore’s law in the Semiconductor industry for the unforeseeable future. There are no
Jatin Chakravarti, Chintan Panchal
semanticscholar   +1 more source

Interactive Client-Side Network Simulation with Dynamic Bandwidth Management and Real-Time 3D Visualization

Jurnal PROCESSOR
Effective network management in dynamic environments necessitates robust tools for real-time analysis and visualization. This paper presents a client-side network simulation designed to model and visualize complex network behaviors, including dynamic ...
Lukman Lukman, Bhanu Sri Nugraha
semanticscholar   +1 more source

Towards Available Bandwidth Estimation for Low-Latency Up-Streaming Amidst Application-Limited Scenarios

Proceedings of the 3rd Workshop on Emerging Multimedia Systems
Low-latency live streaming (LLS) has seen significant growth in recent years. However, real-world data study shows that up-streaming from users to server often experiences stalling or poor video quality.
Zhidong Jia, Li Jiang, Yihang Zhang, Xinggong Zhang, Wei Zhang, Lan Xie, Feng Qian, Leju Yan, Bing Yan, Qiang Ma, Zhou Sha, Wei Yang, Yixuan Ban   +12 more
semanticscholar   +1 more source

Coherence-Aided Memory Bandwidth Regulation

IEEE Real-Time Systems Symposium
With the increasing adoption of PS-PL (Processor System-Programmable Logic) platforms, also known as CPU+FPGA systems, there arises a need for efficient resource management strategies.
Ivan Izhbirdeev, Denis Hoornaert, Weifan Chen, Alexander Zuepke, Youssef Hammad, Marco Caccamo, R. Mancuso   +6 more
semanticscholar   +1 more source

Per-Bank Bandwidth Regulation of Shared Last-Level Cache for Real-Time Systems

IEEE Real-Time Systems Symposium
Modern commercial-off-the-shelf (COTS) multicore processors have advanced memory hierarchies that enhance memory-level parallelism (MLP), which is crucial for high performance.
Connor Sullivan, Alex Manley, Mohammad Alian, Heechul Yun   +3 more
semanticscholar   +1 more source

Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors

International Conference on Parallel Architectures and Compilation Techniques, 2018
In modern processors, prefetching is an essential component for hiding long-latency memory accesses. However, prefetching too aggressively can easily degrade performance by evicting useful data from cache, or by saturating precious memory bandwidth ...
W. Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, I. Hur   +4 more
semanticscholar   +1 more source

Instruction Profiling Based Fetch Throttling for Wasted Dynamic Power Reduction

Symposium on Computer Architecture and High Performance Computing, 2019
In superscalar processors the throughput of the early pipeline stages will impose an upper bound on the throughput of all the subsequent stages. Therefore, to achieve high performance, maximum instruction fetch bandwidth is maintained.
A. Owahid, E. John
semanticscholar   +1 more source

S-Glint: Secure Federated Graph Learning With Traffic Throttling and Flow Scheduling

IEEE Transactions on Green Communications and Networking, 2023
Tao Liu, Pengjie Li, Yu-Zong Gu, Zhou Su
semanticscholar   +1 more source