Results 131 to 140 of about 568,800 (146)

Coherence-Aided Memory Bandwidth Regulation

IEEE Real-Time Systems Symposium
With the increasing adoption of PS-PL (Processor System-Programmable Logic) platforms, also known as CPU+FPGA systems, there arises a need for efficient resource management strategies.
Ivan Izhbirdeev, Denis Hoornaert, Weifan Chen, Alexander Zuepke, Youssef Hammad, Marco Caccamo, R. Mancuso   +6 more
semanticscholar   +1 more source

Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors

International Conference on Parallel Architectures and Compilation Techniques, 2018
In modern processors, prefetching is an essential component for hiding long-latency memory accesses. However, prefetching too aggressively can easily degrade performance by evicting useful data from cache, or by saturating precious memory bandwidth ...
W. Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, I. Hur   +4 more
semanticscholar   +1 more source

Per-Bank Bandwidth Regulation of Shared Last-Level Cache for Real-Time Systems

IEEE Real-Time Systems Symposium
Modern commercial-off-the-shelf (COTS) multicore processors have advanced memory hierarchies that enhance memory-level parallelism (MLP), which is crucial for high performance.
Connor Sullivan, Alex Manley, Mohammad Alian, Heechul Yun   +3 more
semanticscholar   +1 more source

Instruction Profiling Based Fetch Throttling for Wasted Dynamic Power Reduction

Symposium on Computer Architecture and High Performance Computing, 2019
In superscalar processors the throughput of the early pipeline stages will impose an upper bound on the throughput of all the subsequent stages. Therefore, to achieve high performance, maximum instruction fetch bandwidth is maintained.
A. Owahid, E. John
semanticscholar   +1 more source

Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-Based Heterogeneous SoCs

IEEE Transactions on Parallel and Distributed Systems
Commercial embedded systems increasingly rely on heterogeneous architectures that integrate general-purpose, multi-core processors, and various hardware accelerators on the same chip.
Giacomo Valente, Gianluca Brilli, T. D. Mascio, Alessandro Capotondi, P. Burgio, Paolo Valente, A. Marongiu   +6 more
semanticscholar   +1 more source

S-Glint: Secure Federated Graph Learning With Traffic Throttling and Flow Scheduling

IEEE Transactions on Green Communications and Networking, 2023
Tao Liu, Pengjie Li, Yu-Zong Gu, Zhou Su
semanticscholar   +1 more source

{GIFT}: A Coupon Based Throttle-and-Reward Mechanism for Fair and Efficient I/O Bandwidth Management on Parallel Storage Systems

, 2020
Tirthak Patel, Rohan Garg, Devesh Tiwari
openalex  

Quest for high-performance bufferless NoCs with single-cycle express paths and self-learning throttling

Design Automation Conference, 2016
Bhavya K. Daya, L. Peh, A. Chandrakasan
semanticscholar   +1 more source

A Scalable Network Monitoring and Bandwidth Throttling System for Cloud Computing

, 2010
Huysamen Nf, Krzesinski Aes
openalex  

Transient Thermal Analysis for M.2 SSD Thermal Throttling: Detailed CFD Model vs Network-Based Model

Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2018
Hedan Zhang, Hainan Wang, Shay Braha, Ernold Thompson, Ning Ye, Nathan Ai, C. Kao, Nir Amir   +7 more
semanticscholar   +1 more source