Results 91 to 100 of about 13,306 (100)

Design of Reliable SoCs With BIST Hardware and Machine Learning

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
Mehdi Sadi, Gustavo K. Contreras, Jifeng Chen, L. Winemberg, M. Tehranipoor   +4 more
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Design and Implementation of a Power Efficient BIST

International Conference Computing Methodologies and Communication, 2021
According to Moore’s law, the number of transistors in a chip doubles every eighteen months. Since, the number of transistors is increasing, the probability of finding a fault in the transistors also increases.
S. Guru Sharan, S. Jeeshnu, P. Harish Annamalai, S. Haroon Rasheed, E. Prabhu   +4 more
semanticscholar   +1 more source

Google search and stock returns: A study on BIST 100 stocks

, 2020
This study investigates whether there is a relationship between Google search and stock returns after we account for market, size, and value. We analyze weekly data on BIST 100 stocks from 2012 to 2017. Our results reveal that Google search is associated
Cumhur Ekinci, Alican Bulut
semanticscholar   +1 more source

Controller Architecture for Memory BIST Algorithms

2020 IEEE International Students' Conference on Electrical,Electronics and Computer Science (SCEECS), 2020
Design for testability (DFT) help in simplifying the ‘manufacturing tests’ used to detect post fabrication manufacturing defects in an integrated circuits (IC).
Abhas Singh, Gurram Mahanth Kumar, Abhijit Aasti   +2 more
semanticscholar   +1 more source

Deterministic Stellar BIST for In-System Automotive Test

International Test Conference, 2018
With the growing number of very complex safety-critical components used in advanced driver assistance systems and autonomous vehicles, integrated circuits in this area must adhere to stringent requirements for high quality and long-term reliability ...
Yingdi Liu, N. Mukherjee, J. Rajski, S. Reddy, J. Tyszer   +4 more
semanticscholar   +1 more source

Review on LFSR for Low Power BIST

International Conference Computing Methodologies and Communication, 2019
While testing an integrated circuit, large chip size, and excess power dissipation are the major issues. As compared to its working mode, the testing mode power dissipation is very high. In addition to this, the inefficiency of ATE and its time-consuming
M. Mohan, Sunitha S Pillai
semanticscholar   +1 more source

An ADC BIST using on-chip ramp generation and digital ORA

Microelectronics Journal, 2018
This paper presents an on-chip built-in self-test technique for testing an ADC. The conventional test of a mixed signal element has performed through DSP based tester with the help of an arbitrary waveform and a signal digitizer but it is consuming more ...
S. M, Joy Vasantha Rani S P
semanticscholar   +1 more source

XLBIST: X-Tolerant Logic BIST

International Test Conference, 2018
Logic Built-In Self-Test (LBIST) is becoming a requirement for high-complexity, high-reliability ICs which are increasingly used in the automotive field.
P. Wohl, J. Waicukauski, Gregory A. Maston, Jonathon E. Colburn   +3 more
semanticscholar   +1 more source

Implementation of power efficient 8-bit reversible linear feedback shift register for BIST

International Conference on Information Security and Cryptology, 2017
Y. G. P. Kumar, B. Kariyappa, M. Kurian
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Tuning of Multiple Parameters With a BIST System

IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2017
Sahil S. Shah, J. Hasler
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