Results 1 to 10 of about 4,206 (156)

Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches [PDF]

open access: goldIEEE Access, 2022
Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising emerging memory technology for on-chip caches. It has a low read access time and low leakage power. Unfortunately, however, STT-MRAM suffers from its long write latency and high
Yongjun Kim   +4 more
doaj   +2 more sources

A Cache Invalidation Strategy Based on Publish/Subscribe for Named Data Networking [PDF]

open access: goldIEEE Access, 2020
Named Data Networking (NDN) aims to improve the efficiency of data delivery for the Internet. One of the typical characteristics of NDN is ubiquitous caching, that is to say, each network participant in NDN is capable of caching contents.
Yuanzhi Kan   +3 more
doaj   +2 more sources

Hybrid Update/Invalidate Schemes for Cache Coherence Protocols [PDF]

open access: greenНаучный вестник МГТУ ГА, 2015
Appearing in MSTUCA Scientific Bulletin - August 2015, sec:CS; 10 pages, 6 ...
Roman Dovgopol, Matthew Rosonke
  +7 more sources

The satellite network cache placement strategy based on content popularity and node collaboration. [PDF]

open access: yesPLoS ONE
Proposed is a Satellite network cache placement strategy (PNCCP) based on popularity and node cooperation to address the issue of significant delays in end-to-end connectivity due to instability among satellites.
Zhiguo Liu   +3 more
doaj   +2 more sources

Timestamp-based cache invalidation for search engines [PDF]

open access: greenProceedings of the 20th international conference companion on World wide web, 2011
We propose a new mechanism to predict stale queries in the result cache of a search engine. The novelty of our approach is in the use of timestamps in staleness predictions. We show that our approach incurs very little overhead on the system while its prediction accuracy is comparable to earlier works.
Şadiye Alıcı   +4 more
openalex   +4 more sources

Cache Invalidation-Based Optimization in Next Generation Wireless Network: Taxonomy, Review, and Future Directions

open access: goldIEEE Access
Caching has emerged as a common approach utilized to optimize the performance of applications on wireless networks, with the objective of enhancing Quality-of-Service (QoS) metrics.
Rajeev Tiwari   +3 more
doaj   +2 more sources

Constructing Efficient Cache Invalidation Schemes in Mobile Environments [PDF]

open access: yes2007 Third International IEEE Conference on Signal-Image Technologies and Internet-Based System, 2007
[[abstract]]Cache invalidation is an effective approach to maintaining data consistency between the server and mobile clients in a mobile environment.
Chuang, Po-Jen
core   +2 more sources

Cooperative Caching in Vehicular Networks - Distributed Cache Invalidation Using Information Freshness [PDF]

open access: green, 2018
Recent advances in vehicular communications has led to significant opportunities to deploy variety of applications and services improving road safety and traffic efficiency to road users. In regard to traffic management services in distributed vehicular networks, this thesis work evaluates managing storage at vehicles efficiently as cache for moderate ...
Deepak Jayaram
openalex   +3 more sources

An efficient cache invalidation strategy in mobile environments [PDF]

open access: yes18th International Conference on Advanced Information Networking and Applications, 2004. AINA 2004., 2004
[[abstract]]We present a new cache invalidation strategy able to maintain data consistency between the server and mobile clients in an efficient way in mobile communications.[[conferencetype]]國際[[conferencedate]]20040329~20040331[[iscallforpapers]]Y ...
Chuang, Po-Jen
core   +2 more sources

An ACL2 proof of write invalidate cache coherence [PDF]

open access: bronze, 1998
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its own local cache, interact with a global memory via a bus which is snooped by the caches.
J Strother Moore
openalex   +2 more sources

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