Results 41 to 50 of about 4,206 (156)

DCIM: Distributed Cache Invalidation Method for Maintaining Cache Consistency in Wireless Mobile Networks [PDF]

IEEE Transactions on Mobile Computing, 2013
This paper proposes distributed cache invalidation mechanism (DCIM), a client-based cache consistency scheme that is implemented on top of a previously proposed architecture for caching data items in mobile ad hoc networks (MANETs), namely COACS, where special nodes cache the queries and the addresses of the nodes that store the responses to these ...
Kassem Fawaz, Hassan Artail
openaire   +1 more source

Inefficiencies in the Cache Hierarchy: A Sensitivity Study of Cacheline Size with Mobile Workloads [PDF]

, 2015
With the rising number of cores in mobile devices, the cache hierarchy in mobile application processors gets deeper, and the cache size gets bigger.
Emmons, C, Van Laer, A, Wang, W
core  

Lightweight Inter-transaction Caching with Precise Clocks and Dynamic Self-invalidation [PDF]

, 2020
Pulkit A. Misra, Srihari Radhakrishnan, Jeffrey S. Chase, Johannes Gehrke, Alvin R. Lebeck   +4 more
openalex   +1 more source

ParFORM: recent development

, 2005
We report on the status of our project of parallelization of the symbolic manipulation program FORM. We have now parallel versions of FORM running on Cluster- or SMP-architectures.
Baikov, Baikov, Baikov, Baikov, Baikov, Baikov, H.M. Staudenmaier, J.A.M. Vermaseren, M. Tentyukov, Retey, Schwickerath   +10 more
core   +1 more source

Automatic Completion of Distributed Protocols with Symmetry

, 2015
A distributed protocol is typically modeled as a set of communicating processes, where each process is described as an extended state machine along with fairness assumptions, and its correctness is specified using safety and liveness requirements ...
Alur, Rajeev, Raghothaman, Mukund, Stergiou, Christos, Tripakis, Stavros, Udupa, Abhishek   +4 more
core   +1 more source

A Case for Fine-Grain Adaptive Cache Coherence [PDF]

, 2012
As transistor density continues to grow geometrically, processor manufacturers are already able to place a hundred cores on a chip (e.g., Tilera TILE-Gx 100), with massive multicore chips on the horizon.
Devadas, Srinivas, Khan, Omer, Kurian, George   +2 more
core  

Validation of hardware events for successful performance pattern identification in High Performance Computing

, 2017
Hardware performance monitoring (HPM) is a crucial ingredient of performance analysis tools. While there are interfaces like LIKWID, PAPI or the kernel interface perf\_event which provide HPM access with some additional features, many higher level tools ...
Eitzinger, Jan, Hager, Georg, Röhl, Thomas, Wellein, Gerhard   +3 more
core   +1 more source

Overcoming the IOTLB wall for multi-100-Gbps Linux-based networking. [PDF]

PeerJ Comput Sci, 2023
Farshin A, Rizzo L, Elmeleegy K, Kostić D.   +3 more
europepmc   +1 more source

DNS-BC: Fast, Reliable and Secure Domain Name System Caching System Based on a Consortium Blockchain. [PDF]

Sensors (Basel), 2023
Gao T, Dong Q.
europepmc   +1 more source

FragTracer: Real-Time Fragmentation Monitoring Tool for F2FS File System. [PDF]

Sensors (Basel), 2023
Cho M, Kang D.
europepmc   +1 more source