Dynamic Early Dirty Buffer Flush to Reduce Miss Penalty in Solid-State Drives
The design of high-performance solid-state drives (SSDs) have been conducted intensively for various server-based applications, and one of the most popular methods is to use internal memory as cache for NAND flash memory.
Ilhoon Shin
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FASTM: a log-based hardware transactional memory with fast abort recovery [PDF]
Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current HTM systems use either eager or lazy version management.
González Colás, Antonio María +2 more
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A Novel Opportunistic Network Routing Method on Campus Based on the Improved Markov Model
Opportunities networks’ message transmission is significantly impacted by routing prediction, which has been a focus of opportunity network research.
Yumei Cao +5 more
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A Cache Management Scheme for Efficient Content Eviction and Replication in Cache Networks
To cope with the ongoing changing demands of the internet, `in-network caching' has been presented as an application solution for two decades. With the advent of information-centric network (ICN) architecture, `in-network caching' becomes a network level
Muhammad Bilal, Shin-Gak Kang
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CacheMAsT: Cache Management Analysis and Visualization Tool [PDF]
Recent approaches have proposed to empower Internet Service Providers (ISPs) with caching capabilities that can allow them to implement their own cache management strategies and as such have better control over the utilization of their resources. In this
Charalambides, M +3 more
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Decision support tool for web cache management
Web caching is the subject of intense research and development since it seems to be very promising area. Web caching means storing copies of frequently used objects (documents) geographically close to users requesting them to reduce network load ...
Jarosław Pietrzykowski
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Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches [PDF]
The looming breakdown of Moore’s Law and the end of voltage scaling are ushering a new era where neither transistors nor the energy to operate them is free. This calls for a new regime in computer systems, one in which every transistor counts. Caches are
Faldu, Priyank, Grot, Boris
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Two novel cache management mechanisms on CPU-GPU heterogeneous processors
Heterogeneous multicore processors that take full advantage of CPUs and GPUs within the same chip raise an emerging challenge for sharing a series of on-chip resources, particularly Last-Level Cache (LLC) resources.
Huijing Yang, Tingwen Yu
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Optical networking special issue based on selected papers of IEEE ANTS 2015 [PDF]
In Priority-based content processing with Q-routing in Information Centric Networking (ICN), Sibendu Paul, Bitan Banerjee, Amitava Mukherjee and Mrinal K.
Das, N +2 more
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Client-Driven Joint Cache Management and Rate Adaptation for Dynamic Adaptive Streaming over HTTP
Due to the fact that proxy-driven proxy cache management and the client-driven streaming solution of Dynamic Adaptive Streaming over HTTP (DASH) are two independent processes, some difficulties and challenges arise in media data management at the proxy ...
Chenghao Liu +2 more
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