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Enhancing the Malloc System with Pollution Awareness for Better Cache Performance
IEEE Transactions on Parallel and Distributed Systems, 2017Cache pollution, by which weak-locality data unduly replaces strong-locality data, may notably degrade application performance in a shared-cache multicore machine. This paper presents NightWatch, a cache management subsystem that provides general, transparent and low-overhead pollution control to applications.
Xiaofei Liao +4 more
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Intelligent memory manager: Reducing cache pollution due to memory management functions
Journal of Systems Architecture, 2006In this work, we show that data-intensive and frequently-used service functions such as memory allocation and deallocation entangle with application's working set and become a major cause for cache misses. We present our technique that transfers the allocation and de-allocation functions' executions from main CPU to a separate processor residing on ...
Mehran Rezaei, Krishna M. Kavi
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Detection of Cache Pollution Attacks in a Secure Information-Centric Network
2021The future of Internet architectures is information-centric networking structure, to solve the problems of content spoofing attacks in the current Internet structure, making it more useful for IoT-based applications. The ICN is structured with the Internet forwarding state technology which is an advanced technology with a comparative structure. In this
Akanksha Gupta, Priyank Nahar
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Investigating the impact of cache pollution attacks in heterogeneous cellular networks
2017 IEEE 25th International Conference on Network Protocols (ICNP), 2017With the growth of Internet-of-Things, mobile data traffic is expected to increase exponentially. To support this rapid growth, heterogeneous cellular networks comprising of femtocells with storage capabilities along with macrocell base stations have been proposed.
Sibendu Paul +3 more
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A Pollution Alleviative L2 Cache Replacement Policy for Chip Multiprocessor Architecture
2008 International Conference on Networking, Architecture, and Storage, 2008Chip multi-processor exploits both instruction-level and thread-level parallelism effectively. In a typical chip multi-processor architecture, L2 cache is shared by multiple cores. Sharing the L2 cache allows high cache utilization and avoids duplicating cache hardware resources.
Jun Zhang, Xiao-Ya Fan, Song-He Liu
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Achieving non-polluting cache accessing by using data valid tag splitting
Proceedings of 2012 2nd International Conference on Computer Science and Network Technology, 2012Rapid progress of Semiconductor fabrication provides capacious space for IC designs, but unfortunately, the slow development of design ability makes it difficult to utilize the on-chip resource efficiently. At present, more than half of die area of modern microprocessor is inhabited by cache.
Liu Song-He +3 more
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Filtering Cache Pollution by Using Replacement Operation Based on Confidence Estimation
2010 IEEE Fifth International Conference on Networking, Architecture, and Storage, 2010Multi-Core architecture is the development trend of microprocessor architecture, and the “Memory Wall” is the chief obstacle to promote the processor performance. This paper analyzes the key factors affecting performance of memory system in shared L2 cache multi-core on a chip architecture, and believes that cache pollution caused by the speculative ...
Jun Zhang, Kui-zhi Mei, Ji-zhong Zhao
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Improving instruction cache behavior by reducing cache pollution
Proceedings SUPERCOMPUTING '90, 2002R. Gupta, C.-H. Chi
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Detection of Cache Pollution Attack Based on Federated Learning in Ultra-Dense Network
, 2022 Lin Yao, Jia Li, Jing Deng, Guowei Wu
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Reducing Cache Pollution via Dynamic Data Prefetch Filtering
IEEE Transactions on Computers, 2007Xiaotong Zhuang, Hsien-hsin S. Lee
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