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Pho$: A Case for Shared Optical Cache Hierarchies

2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2021
Conventional electronic memory hierarchies are intrinsically limited in their ability to overcome the memory wall due to scaling constraints. Optical caches and interconnects can mitigate these constraints, and enable processors to reach performance and energy efficiency unattainable by purely electronic means.
Haiyang Han   +4 more
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A case for a working-set-based memory hierarchy

Proceedings of the 2nd conference on Computing frontiers, 2005
Modern microprocessor designs continue to obtain impressive performance gains through increasing clock rates and advances in the parallelism obtained via micro-architecture design. Unfortunately, corresponding improvements in memory design technology have not been realized, resulting in latencies of over 100 cycles between processors and main memory ...
Steve Carr 0001, Soner Önder
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