Results 251 to 260 of about 17,631,783 (296)

Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021
The three major tasks in standard cell layout synthesis are transistor folding, transistor placement, and in-cell routing, which are tightly inter-related, but generally performed one at a time to reduce the extremely high complexity of design space.
Kyeonghyeon Baek, Taewhan Kim
semanticscholar   +1 more source

Boosting Pin Accessibility Through Cell Layout Topology Diversification

Asia and South Pacific Design Automation Conference, 2021
As the layout of standard cells is becoming dense, accessing pins is much harder in detailed routing. The conventional solutions to resolving the pin access issue are to attempt cell flipping, cell shifting, cell swapping, and/or cell dilating in the ...
Suwan Kim, Kyeongrok Jo, Taewhan Kim
semanticscholar   +1 more source

Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis

ICCD, 2021
The synthesis of standard cell layouts is largely divided into two tasks namely transistor placement and in-cell routing. Since the result of transistor placement highly affects the quality of in-cell routing, it is crucial to accurately and efficiently ...
Kyeongrok Jo, Taewhan Kim
semanticscholar   +1 more source

A hybrid electromagnetism-like algorithm for dynamic inter/intra-cell layout problem

International Journal of Computer Integrated Manufacturing, 2014
Masoud Rabbani, Reza Tavakkoli-Moghaddam, Fariborz Jolai   +2 more
exaly   +2 more sources

MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020
Multi-row cell structure has become popular for modern designs, especially for the multi-bit flip-flop (MBFF) cells, but has not been under full investigation in previous cell library synthesis researches. In this work, we propose an entire placement and
Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, H. Onodera   +3 more
semanticscholar   +1 more source

An integrated model for solving cell formation and cell layout problem simultaneously considering new situations

Journal of Manufacturing Systems, 2013
Iraj Mahdavi, Vahid Kayvanfar, Ehsan Teymourian   +2 more
exaly   +2 more sources

Standard Cell Layout Generation: Review, Challenges, and Future Works

Asia and South Pacific Design Automation Conference
With the growing demand for VLSI scaling, standard cell library generation becomes crucial process to enhance performance via design technology co-optimization (DTCO) and system technology co-optimization (STCO) exploration.
Chung-Kuan Cheng, Byeonggon Kang, Bill Lin, Yucheng Wang   +3 more
semanticscholar   +1 more source

SO3-Cell: Standard Cell Layout Automation Framework for Simultaneous Optimization of Topology, Placement, and Routing

2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
We propose SO3-Cell, the first automatic standard cell layout generation framework that optimizes three key steps simultaneously using Mixed-Integer Linear Programming (MILP).
Chung-Kuan Cheng, A. B. Kahng, Byeonggon Kang, Seokhyeong Kang, Jakang Lee, Bill Lin   +5 more
semanticscholar   +1 more source

Cell-Flex Metrics for Designing Optimal Standard Cell Layout with Enhanced Cell Layout Flexibility

ACM International Symposium on Physical Design
As physical pitch scaling slows, efforts to match its pace by reducing standard cell height and sacrificing horizontal routing tracks have introduced placement and routing challenges, making the design of high-quality standard cell layouts increasingly ...
Byeonggon Kang, Ying Yuan, Yucheng Wang, Bill Lin, Chung-Kuan Cheng   +4 more
semanticscholar   +1 more source

Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic - and -Values

IEEE Transactions on Electron Devices, 2022
Complementary FET (CFET) is a promising booster for further area reductions in static random-access memory (SRAM) cells. However, the performance degrading by a series of parasitic parameters in these SRAM cells will diminish the scaling benefit ...
Yanna Luo, Lei Cao, Qing-Zhu Zhang, Yu Cao, Zhao-Hao Zhang, Jiaxin Yao, Gangping Yan, Xuexiang Zhang, Weizhuo Gan, Jiali Huo, Haoqing Xu, Guoliang Tian, Weihai Bu, Yongqin Wu, Zhen-Hua Wu, Hua-Xiang Yin   +15 more
semanticscholar   +1 more source