Results 11 to 20 of about 304,090 (304)
Central processing unit of IEC 61131-3-based PLC
Abstract: The article discusses the design process of the central processing unit (CPU) for programmable logic controllers. On the one hand the designed CPU is compatible with IEC 61131-3 standard. On the other hand, the authors attempt to reflect on the possible implementations of the unit by means of FPGA.
P. Mazur, M. Chmiel, Robert Czerwiński
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Graphics Processing Units are immensely powerful processors and for variety applications they outperform the Central Processing Unit, CPU. The recent generations of GPU’s have a flexible architecture than older generations and programming interface more user friendly, which makes them better suited for general purpose programming.
Kristin Paulsen
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Optimal Selection Of Functional Hardware Units For Microprogram Controlled Central Processing Units.
PhD ; Electrical engineering ; University of Michigan, Horace H. Rackham School of Graduate Studies ; http://deepblue.lib.umich.edu/bitstream/2027.42/187365/2/7229088 ...
David Leary Hinshaw
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MIMO Radar Parallel Simulation System Based on CPU/GPU Architecture
The data volume and computation task of MIMO radar is huge; a very high-speed computation is necessary for its real-time processing. In this paper, we mainly study the time division MIMO radar signal processing flow, propose an improved MIMO radar signal
Gaogao Liu +8 more
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Energy-Efficient Federated Learning With Resource Allocation for Green IoT Edge Intelligence in B5G
An edge intelligence-aided Internet-of-Things (IoT) network has been proposed to accelerate the response of IoT services by deploying edge intelligence near IoT devices.
Adeb Salh +7 more
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Reduced-Precision Acceleration of Radio-Astronomical Imaging on Reconfigurable Hardware
Radio telescopes produce large volumes of data that need to be processed to obtain high-resolution sky images. This is a complex task that requires computing systems that provide both high performance and high energy efficiency.
Stefano Corda +7 more
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Reverse Engineering of Intel Microcode Update Structure
Microcode update mechanism have been widely used in modern processors. Due to the implementation details are not public, researchers are prevented from gaining any sort of further understanding currently.
Zhiguo Yang +3 more
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GPU-accelerated compartmental modeling analysis of DCE-MRI data from glioblastoma patients treated with bevacizumab. [PDF]
The compartment model analysis using medical imaging data is the well-established but extremely time consuming technique for quantifying the changes in microvascular physiology of targeted organs in clinical patients after antivascular therapies. In this
Yu-Han H Hsu +3 more
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GPU computing performance analysis on matrix multiplication
The machine learning has been widely used in intelligent data mining. The high-computational complexity of machine learning and huge data volume present challenges to computing platforms.
Zhibin Huang +3 more
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Parallelization Experience with Four Canonical Econometric Models Using ParMitISEM
This paper presents the parallel computing implementation of the MitISEM algorithm, labeled Parallel MitISEM. The basic MitISEM algorithm provides an automatic and flexible method to approximate a non-elliptical target density using adaptive mixtures of ...
Nalan Baştürk +3 more
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