Results 61 to 70 of about 667,612 (106)

AER-RT: Interfície de Xarxa amb Topologia en anell per a SNN Multi-FPGA

Ampliación del protocolo de Bus AER (Addr. Event Rep.) para la transmisión eficiente de spikes en redes neuronales mapeadas en múltiples FPGAs.[ANGLÈS] This thesis presents AER-RT network interface, a network interface designed to work together a ...
Dorta Pérez, Silvestre Taho
core  

Rationale and challenges for optical interconnects to electronic chips

Proceedings of the IEEE, 2000
D. Miller
semanticscholar   +1 more source

Global Analysis of Protein Activities Using Proteome Chips

Science, 2001
H. Zhu, M. Bilgin, R. Bangham, D. Hall, A. Casamayor, Paul Bertone, N. Lan, R. Jansen, S. Bidlingmaier, T. Houfek, T. Mitchell, P. Miller, R. Dean, M. Gerstein, M. Snyder   +14 more
semanticscholar   +1 more source

Securing Network-on-Chips via Novel Anonymous Routing

ACM/IEEE International Symposium on Networks-on-Chips, 2021
Network-on-Chip (NoC) is widely used as an efficient communication architecture in multi-core and many-core System-on-Chips (SoCs). However, the shared communication resources in NoCs, e.g., channels, buffers, and routers might be used to conduct attacks
Amin Sarihi, A. Patooghy, Mahdi M. Hasanzadeh, M. Abdelrehim, Abdel-Hameed A. Badawy   +4 more
semanticscholar   +1 more source

Memristor‐Based Neuromorphic Chips

Advances in Materials
In the era of information, characterized by an exponential growth in data volume and an escalating level of data abstraction, there has been a substantial focus on brain‐like chips, which are known for their robust processing power and energy‐efficient ...
Xuegang Duan, Zelin Cao, Kaikai Gao, Wentao Yan, Siyu Sun, G. Zhou, Zhenhua Wu, Fenggang Ren, Bai Sun   +8 more
semanticscholar   +1 more source

Google's Training Chips Revealed: TPUv2 and TPUv3

IEEE Hot Chips Symposium, 2020
This article consists only of a collection of slides from the author's conference presentation.
Thomas Norrie, Nishant Patil, D. Yoon, George Kurian, Sheng Li, J. Laudon, C. Young, N. Jouppi, David A. Patterson   +8 more
semanticscholar   +1 more source

Security Threats and AI-Based Detection Techniques in IoT Chips

Chips
The rapid expansion of the Internet of Things (IoT) has opened resource-limited devices to novel physical threats, such as Side-Channel Attacks (SCAs) and Hardware Trojans (HTs).
Hiba El Balbali, Anas Abou El Kalam
semanticscholar   +1 more source

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

ACM/IEEE International Symposium on Networks-on-Chips, 2018
Various parallel applications, such as numerical convergent computation and multimedia processing, have intrinsic tolerance to inaccuracies that allow soft errors, i.e. bit flips, on a chip.
Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, M. Koibuchi, H. Amano   +4 more
semanticscholar   +1 more source