Results 221 to 230 of about 89,015 (263)

Uniform Synthesis of Sequential Circuits†

Bell System Technical Journal, 1969
In this paper we consider the synthesis of sequential machines by networks of a fixed module with delay. We show that every binary input n state sequential machine has an isomorphic realization using at most p copies of a module with 2r + 1 inputs, where p is the smaller of ${2r \over 2r - 1} (n^{1+log r^2} + 4n^{1+log r^4)$ and $r2^[n/r]$ . ([x] is
Ullman, J. D., Weiner, P.
openaire   +2 more sources

Logic Synthesis of Approximate Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020
The ability of several important application domains to tolerate inexactness or approximations in a large fraction of their computations has lead to the advent of approximate computing , a new design paradigm that exploits the intrinsic error-resilient nature to optimize computing platforms for energy and performance.
Swagath Venkataramani, Vivek Joy Kozhikkottu, Amit Sabne, Kaushik Roy 0001, Anand Raghunathan   +4 more
openaire   +1 more source

Synthesis of pipelined SRSL circuits

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006
In this paper, we propose a new design methodology for clockless circuits based on the present methodology of clocked circuits. This methodology takes advantage of the maturity of current CAD tools to synthesize new clockless pipelines without disrupting their design flow.
Oreifej, Rashad, Alsharqawi, Abdelhalim, Ejnioui, Abdel   +2 more
openaire   +2 more sources

Synthesis of analog CMOS circuits

Proceedings Tenth International Conference on VLSI Design, 2002
In this paper we describe an efficient method for transistor sizing in cell level analog circuits. An equation based method is used. SPICE quality device models are used and the sizing problem is posed as an optimisation problem. KCL, KVL and matching constraints are taken in to account in the formulation of the optimisation problem without explicitly ...
K. Ravi Shanker, Vinita Vasudevan
openaire   +1 more source

A direct digital period synthesis circuit

IEEE Journal of Solid-State Circuits, 2002
This paper presents a direct digital period synthesis (DDPS) circuit, which combines the DDS' ability to control the frequency, with the speed and accuracy of a delay-locked-loop-based frequency multiplier. The resulting DDPS circuit can synthesize clocks with accurately controlled periods.
Yvon Savaria
exaly   +3 more sources

Synthesis of skewed logic circuits

ACM Transactions on Design Automation of Electronic Systems, 2005
Skewed logic circuits belong to a noise-tolerant high-performance static circuit family. Skewed logic circuits can achieve performance comparable to that of Domino logic circuits but with much lower power consumption. Two factors contribute to the reduction in power.
Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy 0001   +3 more
openaire   +1 more source

Automatic synthesis of asynchronous circuits

Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91, 1991
The synthesis of asynchronous circuits in self-timed systems from the behavior descriptions in STG had been studied in this paper. The novelty of our proposed method is that the whole synthesis is carried out on STG and thereby maintains the problem size proportional to the signal numbers.
Kuan-Jen Lin, Chen-Shang Lin
openaire   +1 more source

Circuit partitioning for logic synthesis

IEEE Journal of Solid-State Circuits, 1991
The authors introduce a circuit partitioning method based on analysis of reconvergent fan-out. A corolla is defined as a set of overlapping reconvergent fan-out regions. The authors partition the circuit into a set of disjoint corollas and use the corollas to resynthesize the circuit.
Sujit Dey, Franc Brglez, Gershon Kedem
openaire   +1 more source

Control circuit synthesis system

Systems and Computers in Japan, 1986
AbstractThis paper presents a systematic and automatic synthesis procedure based on the behavior specifications and the data path. The system automatically determines the control of the data path components and quasiminimizes the hardware complexity of the control circuit.
openaire   +1 more source

Pipeline synthesis of SRSL circuits

2005 12th IEEE International Conference on Electronics, Circuits and Systems, 2005
In this paper, a methodology to synthesize SRSL pipelines has been presented. The synthesis of SRSL pipelines is formulated as an IP problem subject to area and timing constraints for which a heuristic procedure is proposed and applied on six circuits.
Oreifej, Rashad, Alsharqawi, Abdelhalim, Ejnioui, Abdel   +2 more
openaire   +2 more sources