Results 301 to 310 of about 389,945 (331)

Implementation of CMOS oscillator for CMOS SAW resonator

2016 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016
This work presents a design and measurement of pierce oscillator circuit for microelectromechanical system (MEMS) SAW resonator. The pierce oscillator circuit was fabricated using MIMOS 0.35um CMOS technology process. The pierce oscillator circuit provides gain to offset the losses of the resonator.
Jamilah Karim, S Anis Nurashikin Nordin
openaire   +2 more sources

Nanoelectronics devices: More CMOS, fusion CMOS and beyond CMOS

2009 IEEE Asian Solid-State Circuits Conference, 2009
We are facing several difficulties with shrinking LSI chips, such as leakage currents/power consumption, variability, huge costs in R&D and production. Major semiconductor market will be absolutely dependent on further shrinking of Si CMOS transistors with improving transistor structures and lowering drive voltage, increasing wafer diameter and 3D ...
openaire   +2 more sources

ST-CMOS (Stacked Transistors CMOS): A double-poly-NMOS-compatible CMOS technology [PDF]

1981 International Electron Devices Meeting, 1981
A modified double-poly NMOS technology is proposed, providing CMOS structures. The P-channel transistors are made in the second poly layer. The process scheme is standard, except for the laser annealing step. A method of laser annealing of processed [even non-planar] samples is derived, giving rise to a concept of selective annealing.
Jean-Pierre Colinge, E. Demoulin
openaire   +1 more source

Pulsed power supply CMOS-PPS CMOS

Proceedings of 1994 IEEE Symposium on Low Power Electronics, 2002
Low power dissipation using conventional CMOS circuits can be achieved if the power supply lead is ramped repetitively between VDD and VSS. During the power-down edge, the state of the chip is stored on parasitic capacitances. This quasi-static CMOS circuit technique is called PPS (Pulsed Power Supply) CMOS and reduces the power dissipation over ...
openaire   +2 more sources

THE CMO OF CONSEQUENCE

Business Strategy Review, 2010
Do chief marketing officers matter? Some say that CMOs have limited effect on corporate performance and don't add significant value to the firm. D. Eric Boyd, Rajesh Chandy and Marcus Cunha agree that the job in many firms is in great peril, but their research has uncovered why the contributions of some CMOs are invaluable.
D. Eric Boyd, Marcus Cunha, Rajesh Chandy   +2 more
openaire   +2 more sources

A CMOS CCII+

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 2002
A novel CMOS CCII is presented which provides a voltage transfer error better than /spl plusmn/0.1 dB with resistances greater than 25 /spl Omega/. Moreover, the resistance at terminal X is as low as 0.3 /spl Omega/. Thanks to its simple topology, the circuit is particularly suitable as input stage of current feedback operational amplifiers and current
G. Palmisano, Gaetano Palumbo, G. Di Cataldo   +2 more
openaire   +1 more source

Latchup in CMOS

2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual., 2003
Latchup is a failure mode in CMOS circuits that results in either soft failures with a loss of data or logic state, or in extreme cases, a destructive hard failure and permanent loss of the circuit. As isolation widths shrink, device structures become ever more susceptible to both failure modes, unless steps are taken to improve latchup robustness. The
openaire   +2 more sources

CMOS and beyond

Comptes Rendus de l'Académie des Sciences - Series IV - Physics, 2000
Abstract Lithography has played a key role in the scaling of CMOS-based integrated circuits. To fabricate sub-70 nm features, new techniques based on electron projection and extreme ultraviolet radiation are being developed. These and other lithographic solutions are discussed. For the ultimate in scaling, an alternate approach would be to start with
Herb Goronkin, Laura Siragusa, Ray Tsui
openaire   +2 more sources

Groundbounce in CMOS

1994
In this paper, the largest cause of problems in mixed digital/analogue CMOS ic’s is described: substrate voltage bounce. The source of the problem, spikes in supply currents of digital circuits, and the resulting effect on substrate voltage is analysed.
J. Groeneveld, D. Wouter, Douwe T. de Jong   +2 more
openaire   +2 more sources

Beyond CMOS Nanoscale CMOS

2013
[No abstract available]
G. Iannaccone, G. Fiori, REGGIANI, SUSANNA, M. Pala   +3 more
openaire   +1 more source