Results 311 to 320 of about 74,167 (345)

On-chip sampling in CMOS integrated circuits

IEEE Transactions on Electromagnetic Compatibility, 1999
This paper presents a technique for precise crosstalk delay measurement based on on-chip sampling. Results obtained on a test chip fabricated in 0.7-/spl mu/m CMOS technology exhibit a 100% delay increase in a long coupled line configuration.
Ben Dhia, Sonia, Delmas-Bendhia, S., Caignet, Fabrice, Sicard, E., Roca, M.   +4 more
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CMOS integrated circuits for multivalued logic

International Journal of Electronics, 1985
ABSTRACT The use of CMOS integrated circuits in the design of multivalued logic systems is extended. Circuit design of basic quaternary operators (inverters, NAND, NOR, cycling and inverse cycling gates) is presented. These basic quaternary operators can be used as building blocks in four-valued digital systems.
H. T. MOUFTAH, K. C. SMITH
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Millimeter-Wave Integrated Circuits in 65-nm CMOS

IEEE Journal of Solid-State Circuits, 2008
We present the design and measurement results of millimeter-wave integrated circuits implemented in 65-nm baseline CMOS. Both active and passive test structures were measured. In addition, we present the design of an on-chip spiral balun and the transition from CPW to the balun and report transistor noise parameter measurement results at V-band ...
Varonen, M., Kärkkäinen, M., Kantanen, Mikko, Halonen, K.A.I.   +4 more
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AMGIE : a Synthesis Environment for CMOS Analog Integrated Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001
A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization.
Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts   +8 more
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CMOS Integrated Circuits for DNA Sensing

Qatar Foundation Annual Research Conference Proceedings Volume 2016 Issue 1, 2016
BackgroundWith the advance of semiconductor technologies, bio-technological application-specific integrated circuits (ASICs) have become a major trend of the industry. Examples include Microelectrode measurement array systems for in-vitro and in-vivo physiological research at the cellular level [1] [2].
Amine Bermak, Saqib Mohamad
openaire   +1 more source

Novel integrated CMOS sensor circuits

IEEE Transactions on Nuclear Science, 2004
Three novel integrated CMOS active pixel sensor circuits for vertex detector applications have been designed with the goal of increased signal-to-noise ratio and speed. First, a large-area native epitaxial silicon photogate sensor was designed to increase the charge collected per hit pixel and to reduce charge diffusion to neighboring pixels.
S. Kleinfelder, F. Bieser, null Yandong Chen, R. Gareus, H.S. Matis, M. Oldenburg, F. Retiere, H.G. Ritter, H.H. Wieman, E. Yamamoto   +9 more
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CMOS/bipolar linear integrated circuits

1974 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1974
A simple, high-performance operational amplifier using an economical monolithic CMOS/bipolar process will be described, and circuit components, layout and performance discussed.
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Reverse engineering of CMOS integrated circuits

2016
New methods for automated visual recognition of metal interconnect technological layers of integrated circuits are presented. Image processing and analysis algorithms are used in these methods to extract interconnect structure locations and dimensions.
Masalskis, Giedrius, Navickas, Romualdas
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Differential testing of CMOS integrated circuits

2009
As CMOS technologies scale down, background leakage current increases inexorably, primarily due to device sub-threshold leakage. As a result, conventional single-threshold pass/fail IDDQ testing may no longer be valid for deep sub-micron technology. A number of alternatives to single threshold IDDQ testing have been proposed.
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Hybrid CMOS/Molecular Integrated Circuits

2009
Despite revolutionary advances enabled by process scaling in the past few decades, CMOS silicon technology is likely to run out of steam in the next 10–15 years [1]. The prospect of nanoelectronics offers many potential alternatives; single electron tunneling (SET) devices, resonant tunneling diodes (RTD), rapid single flux quantum logic (RSFQ), spin ...
M. R. Stan, G. S. Rose, M. M. Ziegler
openaire   +1 more source