Results 281 to 290 of about 37,010 (319)
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Writing a compilers compiler in APL
ACM SIGAPL APL Quote Quad, 1998This paper describes the special capabilities of APL2 for the construction of compilers and translator writing systems (TWS). To that purpose, a TWS has been written in APL2, which takes as input a complete description of a language including an attribute grammar, in extended Backus normal form, and the semantic function associated to each rule of the ...
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MUG1 - an incremental compiler-compiler
Proceedings of the annual conference on - ACM 76, 1976MUG1 is a compiler generating system developed and implemented at the Technical University of Munich. The structure of the system and the concepts used in the compiler description are presented. Special emphasis is laid on the use of MUG1 as a tool for the incremental design of programming languages and the construction of their compilers in parallel.
Harald Ganzinger +2 more
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Using the CDL compiler-compiler
1974In this sequence of lectures one compiler compiler is going to be highlighted by means of somewhat larger examples, preceded by a discussion of ideas underlying it.
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2013
Continuing from the last chapter, the Hello World program is now complete and ready to be compiled and run. You can do this by going to the Debug menu and clicking on Start Without Debugging (Ctrl + F5). Visual Studio then compiles and runs the application which displays the text in a console window.
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Continuing from the last chapter, the Hello World program is now complete and ready to be compiled and run. You can do this by going to the Debug menu and clicking on Start Without Debugging (Ctrl + F5). Visual Studio then compiles and runs the application which displays the text in a console window.
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ACM SIGPLAN Notices, 1982
In this paper we discuss about another approch: Compiler Chip , which is a VLSI implementation of a compiler. Constructing a compiler by a few VLSI chip, the computer manufacturer can deliver compilers by sets of VLSI chips, and these chips are installed in a intelligent terminal in order to remove the compilation ...
Masaharu Hirayama, Akira Fusaoka
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In this paper we discuss about another approch: Compiler Chip , which is a VLSI implementation of a compiler. Constructing a compiler by a few VLSI chip, the computer manufacturer can deliver compilers by sets of VLSI chips, and these chips are installed in a intelligent terminal in order to remove the compilation ...
Masaharu Hirayama, Akira Fusaoka
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Proceedings of the 2002 ACM SIGPLAN workshop on Partial evaluation and semantics-based program manipulation - PEPM '02, 2002
Traditional compilers compile and optimize files separately, making worst-case assumptions about the program context in which a file is to be linked. More aggressive compilation architectures perform cross-file interprocedural or whole-program analyses, potentially producing much faster programs but substantially increasing the cost of compilation ...
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Traditional compilers compile and optimize files separately, making worst-case assumptions about the program context in which a file is to be linked. More aggressive compilation architectures perform cross-file interprocedural or whole-program analyses, potentially producing much faster programs but substantially increasing the cost of compilation ...
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Compilation reuse and hybrid compilation
ACM SIGPLAN Notices, 2006Compiling hardware models to machine code poses some unusual problems. While compilers for traditional programming languages are well understood, they tend to take very long to compile the C code generated from hardware models. The code generated from hardware models, unlike in the inputs seen by traditional compilers, have too many simple routines ...
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ACM SIGAPL APL Quote Quad, 1979
The overall design of an APL compiler which achieves significant savings of temporary storage is outlined. A graphical intermediate representation for APL expressions is described. Transformations which may be applied to this intermediate representation to select improved array access orders are presented with examples of the storage savings obtained.
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The overall design of an APL compiler which achieves significant savings of temporary storage is outlined. A graphical intermediate representation for APL expressions is described. Transformations which may be applied to this intermediate representation to select improved array access orders are presented with examples of the storage savings obtained.
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Russian Studies in Literature, 2014
The relevance of laughter as coercion and even as a mechanism of intimidation and control is discussed in the context of Soviet humor.
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The relevance of laughter as coercion and even as a mechanism of intimidation and control is discussed in the context of Soviet humor.
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