Results 81 to 90 of about 4,307,634 (306)
An all‐in‐one analog AI accelerator is presented, enabling on‐chip training, weight retention, and long‐term inference acceleration. It leverages a BEOL‐integrated CMO/HfOx ReRAM array with low‐voltage operation (<1.5 V), multi‐bit capability over 32 states, low programming noise (10 nS), and near‐ideal weight transfer.
Donato Francesco Falcone +11 more
wiley +1 more source
Comparison of Parallelization Strategies for Min-Sum Decoding of Irregular LDPC Codes
Low-Density Parity-Check (LDPC) codes are powerful error correcting codes. LDPC decoders have been implemented as efficient error correction codes on dedicated VLSI hardware architectures in recent years.
Hua Xu +5 more
doaj +1 more source
International audienceCUDA (Compute Unified Device Architecture) is an efficient architecture developed by NVIDIA to compute parallel algorithms on Graphic Processing Unit (GPU).
Domenger, Jean-Philippe +2 more
core
Benchmarking and modelling of POWER-7, Westmere, BG/P, and GPUs : an industry case study [PDF]
This paper introduces an industry strength, multi-purpose, benchmark: Shamrock. Developed at the Atomic Weapons Establishment (AWE), Shamrock is a two dimensional (2D) structured hydrocode; one of its aims is to assess the impacts of a change in hardware,
Turland, D. +7 more
core +1 more source
Edible electronics needs integrated logic circuits for computation and control. This work presents a potentially edible printed chitosan‐gated transistor with a design optimized for integration in circuits. Its implementation in integrated logic gates and circuits operating at low voltage (0.7 V) is demonstrated, as well as the compatibility with an ...
Giulia Coco +8 more
wiley +1 more source
DNA strands are employed both as dynamic linkers and nanoscale templates for the integration of Ag2S nanoparticles on MoS2, which in turn imparted photothermal responsiveness; this feature permits the selective cargo (fluorophore, quantum dots or an enzyme) release from the MoS2 surface in response to local heat induced by light irradiation.
Kai Chen +3 more
wiley +1 more source
Compute Unified Device Architecture (CUDA) is a parallel computing platform developed by Nvidia for increase speed of graphics by usage of parallel mode for processes calculation. The success of this solution has opened technology General-Purpose Graphic
Grzeszczuk A., Kowalski S.
doaj +1 more source
Counterion Dependent Side‐Chain Relaxation Stiffens a Chemically Doped Thienothiophene Copolymer
Oxidation of a thienothiophene copolymer, p(g3TT‐T2), via different doping strategies and dopant molecules resulted in materials with similar oxidation levels and a high electrical conductivity of ≈100 S cm−1. However, mechanical properties varied significantly, with sub‐glass transition temperatures and elastic moduli spanning from –44°C to –3°C and ...
Mariavittoria Craighero +12 more
wiley +1 more source
A VLSI Array Architecture for Realization of DFT, DHT, DCT and DST
A unified array architecture is described for computation of DFT, DHT, DCT and DST using a modified CORDIC (CoOrdinate Rotation DIgital Computer) arithmetic unit as the basic Processing Element (PE).
Dhar, Anindya Sunder +2 more
core +1 more source
Propagation of Cylindrical Vector Laser Beams in Turbid Tissue-Like Scattering Media
We explore the propagation of the cylindrical vector beams (CVB) in turbid tissue-like scattering medium in comparison with the conventional Gaussian laser beam.
Alexander Doronin +4 more
doaj +1 more source

