Results 11 to 20 of about 28,084 (193)
Concatenated Forward Error Correction With KP4 and Single Parity Check Codes [PDF]
Journal of Lightwave Technology, 2023 Concatenated forward error correction is studied using an outer KP4 Reed-Solomon code with hard-decision decoding and inner single parity check (SPC) codes with Chase/Wagner soft-decision decoding. Analytical expressions are derived for the end-to-end frame and bit error rates for transmission over additive white Gaussian noise channels with binary ...
Diego Lentner +5 more
+6 more sources
Guaranteed error correction rate for a simple concatenated coding scheme with single-trial decoding
IEEE Transactions on Information Theory, 2000 Summary: We consider a concatenated coding scheme using a single inner code, a single outer code, and a fixed single-trial decoding strategy that maximizes the number of errors guaranteed to be corrected in a concatenated codeword. For this scheme, we investigate whether maximizing the guaranteed error correction rate, i.e., the number of correctable ...
Weber, J.H. (author) +1 more
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Error Correction for Physical Unclonable Functions Using Generalized Concatenated Codes
, 2014 Physical Unclonable Functions can be used for secure key generation in cryptographic applications. It is explained how methods from coding theory must be applied in order to ensure reliable key regeneration. Based on previous work, we show ways how to obtain better results with respect to error probability and codeword length. Also, an example based on
Müelich, Sven +4 more
+6 more sources
Study on Error Correction Capability of Simple Concatenated Polar Codes
International Journal on Advanced Science, Engineering and Information Technology, 2020 Polar codes ware mathematically proven to achieve the Shannon limit, where the error probability is reduced with the help of frozen bits. Since the frozen bits are detrimental in terms of transmission efficiency, this paper investigates the importance of the frozen bits and the possibility of being replaced by other protected bits via a concatenation ...
Khoirul Anwar +3 more
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SPIIRAS Proceedings, 2019 One of the approaches to organization of error correcting coding for multilevel flash memory is based on concatenated construction, in particular, on multidimensional lattices for inner coding. A characteristic feature of such structures is the dominance of the complexity of the outer decoder in the total decoder complexity.
Feliks Taubin, Andrey Trofimov
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Concatenated Coding for GNSS Signals in Urban Environments
Applied Sciences, 2020 This work investigated concatenated coding schemes for Global Navigation Satellite System (GNSS) signals in order to increase their error correction capability in urban environments.
Jing Ke +4 more
doaj +1 more source
Concatenating Decoherence-Free Subspaces with Quantum Error Correcting Codes [PDF]
Physical Review Letters, 1999 An operator sum representation is derived for a decoherence-free subspace (DFS) and used to (i) show that DFSs are the class of quantum error correcting codes (QECCs) with fixed, unitary recovery operators, and (ii) find explicit representations for the Kraus operators of collective decoherence.
K. B. Whaley +2 more
openaire +3 more sources
Code-Based Cryptography With Generalized Concatenated Codes for Restricted Error Values
IEEE Open Journal of the Communications Society, 2022 Code-based cryptosystems are promising candidates for post-quantum cryptography. Recently, generalized concatenated codes over Gaussian and Eisenstein integers were proposed for those systems. For a channel model with errors of restricted weight, those q-
Johann-Philipp Thiers +1 more
doaj +1 more source
An Improved Marker Code Scheme Based on Nucleotide Bases for DNA Data Storage
Applied Sciences, 2023 Due to the rapid growth in the global volume of data, deoxyribonucleic acid (DNA) data storage has emerged. Error correction in DNA data storage is a key part of this storage technology.
Jian Tong, Guojun Han, Yi Sun
doaj +1 more source
Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction [PDF]
International Journal of Electronics and Telecommunications, 2020 This paper presents the design of a compact protocol for fixed-latency, high-speed, reliable, serial transmission between simple field-programmable gate arrays (FPGA) devices.
Michał Kruszewski +1 more
doaj +1 more source