Results 261 to 270 of about 60,468 (320)
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Real-Time FPGA Investigation of Potential FEC Schemes for 800G-ZR/ZR+ Forward Error Correction
Journal of Lightwave Technology, 2023Forward error correction (FEC) performance down to 1e-15 bit error rate (BER) of a open FEC code (OFEC), which was recently proposed for the 800G inter-data center interconnect (DCI) standard, is verified with a 100-piece-FPGA implementation at a record ...
Weiming Wang +8 more
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Concatenated Synchronization Error Correcting Code with Designed Markers
2019 IEEE 5th International Conference on Computer and Communications (ICCC), 2019A concatenated code with designed markers is proposed to detect and correct both synchronization and substitution errors. The inner decoder is effective in maintaining synchronization at codeword boundaries with the help of designed markers. The outer conventional error correcting code is used to provide adequate error correcting capability.
Tianbo Xue, C.M. Francis Lau
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Error-Correcting WOM Codes: Concatenation and Joint Design
IEEE Transactions on Information Theory, 2019We construct error-correcting write-once memory (WOM) codes that guarantee correction of any specified number of errors in $q$ -level memories. The constructions use suitably designed short $q$ -ary WOM codes and concatenate them with outer error-correcting codes over different alphabets using suitably designed mappings.
Amit Solomon, Yuval Cassuto
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Concatenation of error-correcting codes and multiple transmit antennas
2000 IEEE International Symposium on Information Theory (Cat. No.00CH37060), 2002Many wireless systems today employ error correcting coding. Adding transmit diversity may further improve the performance. We study the options to achieve the goal without significant change to the existing systems.
null Xiaodong Li +2 more
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Application of erasure error correction to concatenated partial-response channel code
1999 IEEE International Conference on Communications (Cat. No. 99CH36311), 2003 Erasure error correction based on List-SOVA has been applied to partial-response channel code for high-density magnetic recording. Soft-output information extracted from modified EEPR4ML is used. To achieve as high a total coding rate as possible, a 16/17MTR(3;11) code and a rate 544/561 cyclic redundancy check code (CRCC) are combined.
Naoto Kobayashi +3 more
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Randomized multi-label subproblems concatenation via error correcting output codes
Neurocomputing, 2020Abstract In this paper, we study the error correcting output codes for multi-label classification problems. Imbalance problem is very common in multi-label task and it has not been effectively solved yet. In previous works, base classifiers are learned from the same pool of training data which may lead to similar classifiers, especially when a large ...
Jincheng Shan +4 more
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Concatenated permutation block codes for correcting single transposition errors
2014 IEEE Information Theory Workshop (ITW 2014), 2014Permutation codes are advantageous due to their favourable symbol diversity properties and are applied in flash memories combined with rank modulation. Codebooks traditionally consist of permutations with specific distance properties. A class of permutation codes was presented where a codeword consists of a sequence or concatenation of permutations ...
Reolyn Heymann +3 more
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Turbo product code decoding for concatenated space-time error correcting codes
2009 IEEE 20th International Symposium on Personal, Indoor and Mobile Radio Communications, 2009This paper presents iterative decoding structures for concatenated space-time error correcting codes (STECCs), based on the turbo product code decoding algorithm. Thanks to linear combinations of forward error correcting (FEC) codewords, established to create a space-time redundancy, a product code is reconstructed from concatenated STECC ensuring at ...
Mohamad Sayed Hassan, Karine Amis
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An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking
IEEE Computer Society Annual Symposium on VLSI, 2022The RS(544,514) code with an error correction capacity of 15, also known as KP4 forward error code (FEC), has been adopted by IEEE Ethernet standards since it can make a good trade-off between complexity and decoding performance [1].
Le Yang +4 more
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A Novel Interleaving Scheme for Concatenated Codes on Burst-Error Channel
Asia-Pacific Conference on Communications, 2022With the rapid development of Ethernet, RS (544, 514) (KP4-forward error correction), which was widely used in high-speed Ethernet standards for its good performance-complexity trade-off, may not meet the demands of next-generation Ethernet for higher ...
Lu Liu, Suwen Song, Zhongfeng Wang
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