Results 111 to 120 of about 100,046 (164)

Development of a high-performance in-memory database architecture for intelligent video surveillance in critical patient care. [PDF]

Front Digit Health
Veerapaneni RK, Delhibabu R, Subbotin A, Zhukova N.   +3 more
europepmc   +1 more source

Configural Memory with Network Reinforcement Learning

, 2006
Gray, Wayne D., Veksler, Vladislav D.
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Process variation impact on FPGA configuration memory

2009 10th International Symposium on Quality of Electronic Design, 2009
The impact of process local variation on FPGA configuration memory is studied in this paper. Memory cell stability is examined by simulations and experiments on 65nm and 45nm processes. A statistical simulation method, which correlates closely with product silicon, has been developed.
Yanzhong Xu, Lin-Shih Liu, Mark Chan, Jeff Watt   +3 more
exaly   +2 more sources

Architecture of centralized field-configurable memory

Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, 1995
As the capacities of FPGAs grow, it becomes feasible to implement the memory portions of systems directly on an FPGA together with logic. We believe that such an FPGA must contain specialized architectural support in order to implement memories efficiently.
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic   +2 more
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Configurable architecture for memory BIST

2011 9th East-West Design & Test Symposium (EWDTS), 2011
The number of memory components in today's chips is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture.
Atieh Lotfi, Parisa Kabiri, Zainalabedin Navabi   +2 more
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Enhanced configurable parallel memory architecture

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools, 2003
Contemporary multimedia processors and applications are increasingly limited by their data accessing capabilities. However, the designed Configurable Parallel Memory Architecture (CPMA) alleviates these multimedia data accessing requirements; achieving significant performance improvements over traditional memory architectures.
Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen   +3 more
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Energy aware memory architecture configuration

ACM SIGARCH Computer Architecture News, 2004
In the context of battery-driven embedded systems, reducing energy while maintaining performance is one of today's challenges. The on-chip memory count for a great part of the whole system consumption, especially for images and video processing applications that make heavy use of large memory data size.In this paper, we present new technique for ...
Hanene Ben Fradj, Asmaa el Ouardighi, Cécile Belleudy, Michel Auguin   +3 more
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Memory Hierarchy Configuration Analysis

IEEE Transactions on Computers, 1978
This paper presents an analytical study of speed-cost tradeoffs in memory hierarchy design. It develops an optimization criterion by which average access time, i. e., memory system delay, is minimized under a cost constraint for a hierarchy with given memory sizes and access probabilities.
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Configurable Data Memory for Multimedia Processing

Journal of Signal Processing Systems, 2007
In modern multimedia applications, memory bottleneck can be alleviated with special stride data accesses. Data elements in stride access can be retrieved in parallel with parallel memories, in which the idea is to increase memory bandwidth with several memory modules working in parallel and feed the processor with only necessary data.
Eero Aho, Jarno Vanne, Timo D. Hämäläinen   +2 more
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Configurable memory organisation for communication applications

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools, 2003
A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done by controlling the DSP processor's access to memory buses with an external processor and switches.
Pelkonen, Antti, Roivainen, Jussi, Soininen, Juha-Pekka   +3 more
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