Results 201 to 210 of about 101,017 (262)

Standalone RFID Access Control System with Data-Integrity Verification Capabilities. [PDF]

Sensors (Basel)
Popa V, Petrariu AI, Mutescu PM, Maftei AA, Lavric A.   +4 more
europepmc   +1 more source

Hybrid Nature-Inspired Optimization for the Cell Formation Problem with Machine Reliability and Alternative Routings. [PDF]

Biomimetics (Basel)
Figueroa-Torrez P, Crawford B, Durán O, Jurado-Camacho M, Andrade Roque DR, Vargas-Gutierrez A, Cisternas-Caneo F.   +6 more
europepmc   +1 more source

Coupled polarization dynamics and charge tunneling enable reconfigurable heterojunctions. [PDF]

Nat Commun
Li C, Yu T, Zhang Z, Deng Q, Hui F, Wang Z, Lanza M, Sun L.   +7 more
europepmc   +1 more source

Gungnir codec enabling high error-tolerance and low-redundancy DNA storage through substantial computing power. [PDF]

Nat Commun
Zhang J, Chen L, Sun J, Li S, Zhou Y, Wu Z, Li C, Zheng Z, Luo R.   +8 more
europepmc   +1 more source

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Configurable architecture for memory BIST

2011 9th East-West Design & Test Symposium (EWDTS), 2011
The number of memory components in today's chips is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture.
Atieh Lotfi, Parisa Kabiri, Zainalabedin Navabi   +2 more
openaire   +1 more source

Architecture of centralized field-configurable memory

Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, 1995
As the capacities of FPGAs grow, it becomes feasible to implement the memory portions of systems directly on an FPGA together with logic. We believe that such an FPGA must contain specialized architectural support in order to implement memories efficiently.
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic   +2 more
openaire   +1 more source

Memory Hierarchy Configuration Analysis

IEEE Transactions on Computers, 1978
This paper presents an analytical study of speed-cost tradeoffs in memory hierarchy design. It develops an optimization criterion by which average access time, i. e., memory system delay, is minimized under a cost constraint for a hierarchy with given memory sizes and access probabilities.
openaire   +2 more sources

Enhanced configurable parallel memory architecture

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools, 2003
Contemporary multimedia processors and applications are increasingly limited by their data accessing capabilities. However, the designed Configurable Parallel Memory Architecture (CPMA) alleviates these multimedia data accessing requirements; achieving significant performance improvements over traditional memory architectures.
Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen   +3 more
openaire   +1 more source

Configuring Memory in the Buffyverse

2015
In this chapter, I look more closely at transmedia fandom through an examination of audience engagement with the Buffy the Vampire Slayer crossmedial franchise. Originating as a feature film, Buffy evolved into a popular and well-regarded television series that in turn produced its own televisual spinoff and spawned a wide range of other media such as ...
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Energy aware memory architecture configuration

ACM SIGARCH Computer Architecture News, 2004
In the context of battery-driven embedded systems, reducing energy while maintaining performance is one of today's challenges. The on-chip memory count for a great part of the whole system consumption, especially for images and video processing applications that make heavy use of large memory data size.In this paper, we present new technique for ...
Hanene Ben Fradj, Asmaa el Ouardighi, Cécile Belleudy, Michel Auguin   +3 more
openaire   +1 more source