Results 21 to 30 of about 100,046 (164)
Exploring FPGA Logic Block Architecture for Reduced Configuration Memory
Advances in Electrical and Computer Engineering, 2022 The reduction of reconfiguration delay, during the partial dynamic reconfiguration of FPGAs, is important. In this context, the bitstream compression technique is one of the widely used techniques. These compression techniques only minimize the size of
HUSSAIN, F. +3 more
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Enhancement of Deep Neural Network Recognition on MPSoC with Single Event Upset
Micromachines, 2023 This paper introduces a new finding regarding single event upsets (SEUs) in configuration memory, and their potential impact on enhancing the performance of deep neural networks (DNNs) on the multiprocessor system on chip (MPSoC) platform. Traditionally,
Weitao Yang +8 more
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Advanced Electronic Materials, 2023 A hole‐type vertical structure is adopted to fabricate a vertically stacked resistive switching random access memory (ReRAM) array. The vertical configuration is more advantageous in lowering the process cost and increasing integration density than the ...
Seung Soo Kim +7 more
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Entanglement Dynamics of Coupled Quantum Oscillators in Independent NonMarkovian Baths
Entropy, 2022 This work strives to better understand how the entanglement in an open quantum system, here represented by two coupled Brownian oscillators, is affected by a nonMarkovian environment (with memories), here represented by two independent baths each ...
Jen-Tsung Hsiang +2 more
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Cognition and Memory in the Withdrawal of the Self. Reflection from Paul Ricœur
RHS Revista Humanismo y Sociedad, 2023 The objective of this article is to present an analysis of memory and its place in the configuration of personal identity. It is argued that personal identity implies the construction of a reflexive memory, and that cognition connects with Paul Ricœur's ...
Yeny Leydy Osorio Sánchez
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Brain and Behavior, 2023 Introduction When we memorize simultaneous items, we not only store information about specific items and/or their locations but also how items are related to each other.
Raju P. Sapkota +5 more
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Vision, 2023 Visuospatial working memory is often assessed using the Corsi block-tapping task where set size is used to estimate capacity. It is well established that characteristics of the Corsi task path configuration such as length, crossings, and angles influence
Anthony Tapper, Ewa Niechwiej-Szwedo
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Memory Chips with Adjustable Configurations [PDF]
VLSI Design, 1998 In this paper, we present the concept of Field Programmable Memory Cell Arrays (FPMCAs) as the memory counterpart to Field Programmable Gate Arrays which have proved their utility in design and rapid prototyping. Principles of dynamic reconfigurability using programmable logic and programmable interconnect are incorporated into random access memories ...
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Journal of Materials Research and Technology, 2023 In the present work, minor Sc addition was employed to control the microstructural features, further optimizing the mechanical/functional performances of Ti–V–Al based shape memory alloy.
Xiaoyang Yi +7 more
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Memory Map: A Multiprocessor Cache Simulator
Journal of Electrical and Computer Engineering, 2012 Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major
Shaily Mittal, Nitin
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