Results 21 to 30 of about 101,017 (262)
Memory Map: A Multiprocessor Cache Simulator
Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major
Shaily Mittal, Nitin
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In systems with local gauge symmetries, the memory effect corresponds to traces inscribed on a suitable probe when a pure gauge configuration at infinite past dynamically evolves to another pure gauge configuration at infinite future.
Hamid Afshar +2 more
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Reorganization of spatial configurations in visual working memory: A matter of set size?
Humans process single objects in relation to other simultaneously maintained objects in visual working memory. This interdependence is called spatial configuration.
J David Timm, Frank Papenmeier
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FPGA-based protein sequence alignment : A review
Sequence alignment have been optimized using several techniques in order to accelerate the computation time to obtain the optimal score by implementing DP-based algorithm into hardware such as FPGA-based platform.
Md. Isa Mohd. Nazrin +7 more
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Optical Multi-Context Blind Scrubbing for Field Programmable Gate Arrays
This paper presents aproposal of a new optical multi-context blind scrubbing that can not only increase the soft-error tolerance of the configuration memory of field programmable gate arrays (FPGAs) but also support high-speed dynamic reconfiguration ...
Yusuke Takaki, Minoru Watanabe
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Description of hardware configurations of guest systems in QEMU emulator as separate text files
QEMU is an open-source full system emulator based on the dynamic binary translation approach. QEMU emulates a complete hardware environment including CPUs, peripheral devices (VGA cards, network interfaces, IDE controllers, sound and USB components, and ...
O. V. Goremykin
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Implications of NVM Based Storage on Memory Subsystem Management
Recently, non-volatile memory (NVM) has advanced as a fast storage medium, and legacy memory subsystems optimized for DRAM (dynamic random access memory) and HDD (hard disk drive) hierarchies need to be revisited.
Hyokyung Bahn, Kyungwoon Cho
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The participation of older people in technology development is an ambivalent field: while promising a better fit between users and technology, it still is challenging for both the project and for older users.
Cordula Endter
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Three abstraction levels based low overhead scheme of multiple bit upsets mitigation for FPGA
Commercial-off-the-shelf(COTS) FPGAs are often advocated as the only solution to the increasing performance requirements in space applications. It also increases the circuit sensitivity to multiple bit upsets(MBU), thus specific design techniques must be
Zhang Xiaolin, Ding Lei, Gu Liming
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An Optimized Frame-Driven Routing Algorithm for Reconfigurable SRAM-Based FPGAs
Reconfigurable SRAM-based Field Programmable Gate Arrays (FPGAs) are everyday more attractive due to their high integration, performance, flexibility, and upgradability.
Ludovica Bozzoli, Luca Sterpone
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