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CPU Accounting for Multicore Processors [PDF]
IEEE Transactions on Computers, 2012 In single-threaded processors and Symmetric Multiprocessors the execution time of a task depends on the other tasks it runs with (the workload), since the Operating System (OS) time shares the CPU(s) between tasks in the workload. However, the time accounted to a task is roughly the same regardless of the workload in which the task runs in, since the ...
Carlos Luque +5 more
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Proceedings of the eighteenth international symposium on Software testing and analysis, 2009 A CPU emulator is a software that simulates a hardware CPU. Emulators are widely used by computer scientists for various kind of activities (e.g., debugging, profiling, and malware analysis). Although no theoretical limitation prevents to develop an emulator that faithfully emulates a physical CPU, writing a fully featured emulator is a very ...
L. Martignoni +3 more
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CPU Bugs, CPU Backdoors and Consequences on Security
Journal in Computer Virology, 2008In this paper, we present the security implications of x86 processor bugs or backdoors on operating systems and virtual machine monitors. We will not try to determine whether the backdoor threat is realistic or not, but we will assume that a bug or a backdoor exists and analyze the consequences on systems.
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Proceedings of the 25th Symposium on Operating Systems Principles, 2015
Testing the hypervisor is important for ensuring the correct operation and security of systems, but it is a hard and challenging task. We observe, however, that the challenge is similar in many respects to that of testing real CPUs. We thus propose to apply the testing environment of CPU vendors to hypervisors.
Nadav Amit +4 more
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Testing the hypervisor is important for ensuring the correct operation and security of systems, but it is a hard and challenging task. We observe, however, that the challenge is similar in many respects to that of testing real CPUs. We thus propose to apply the testing environment of CPU vendors to hypervisors.
Nadav Amit +4 more
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Proceedings of the 3rd VLDB Workshop on In-Memory Data Mangement and Analytics, 2015
Modern processors employ sophisticated techniques such as speculative or out-of-order execution to hide memory latencies and keep their pipelines fully utilized. However, these techniques introduce high complexity and variance to query processing. In particular, these techniques are transparent to DBMS operations since they are managed by processors ...
Steffen Zeuch, Johann-Christoph Freytag
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Modern processors employ sophisticated techniques such as speculative or out-of-order execution to hide memory latencies and keep their pipelines fully utilized. However, these techniques introduce high complexity and variance to query processing. In particular, these techniques are transparent to DBMS operations since they are managed by processors ...
Steffen Zeuch, Johann-Christoph Freytag
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International Journal on Artificial Intelligence Tools, 1997
In this paper, the methodology of using fuzzy logic techniques to improve the performance of CPU scheduling is concisely proposed. To make CPU work efficiently in the multiple-factor environment, we developed a fuzzy CPU scheduling algorithm to deal with the fuzziness of CPU scheduling. The simulations of different CPU scheduling algorithms have shown
Yan-Qing Zhang 0001, Abraham Kandel
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In this paper, the methodology of using fuzzy logic techniques to improve the performance of CPU scheduling is concisely proposed. To make CPU work efficiently in the multiple-factor environment, we developed a fuzzy CPU scheduling algorithm to deal with the fuzziness of CPU scheduling. The simulations of different CPU scheduling algorithms have shown
Yan-Qing Zhang 0001, Abraham Kandel
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Proceedings of the second USENIX symposium on Operating systems design and implementation, 1996
Traditional processor scheduling mechanisms in operating systems are fairly rigid, often supportingonly one fixed scheduling policy, or, at most, a few “scheduling classes” whose implementations are closely tied together in the OS kernel. This paper presents CPU inheritance scheduling, a novel processor scheduling framework in which arbitrary threads ...
Bryan Ford, Sai Susarla
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Traditional processor scheduling mechanisms in operating systems are fairly rigid, often supportingonly one fixed scheduling policy, or, at most, a few “scheduling classes” whose implementations are closely tied together in the OS kernel. This paper presents CPU inheritance scheduling, a novel processor scheduling framework in which arbitrary threads ...
Bryan Ford, Sai Susarla
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Microarchitecture of HaL's CPU
Digest of Papers. COMPCON'95. Technologies for the Information Superhighway, 2002The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order and are later committed in order. The PM1 CPU maintains precise state. The processor has a higher level
Niteen Patkar +8 more
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Performance Traps in OpenCL for CPUs
2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, 2013With its design concept of cross-platform portability, OpenCL can be used not only on GPUs (for which it is quite popular), but also on CPUs. Whether porting GPU programs to CPUs, or simply writing new code for CPUs, using OpenCL brings up the performance issue, usually raised in one of two forms: "OpenCL is not performance portable!" or "Why using ...
Jie Shen 0003 +3 more
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IEEE Spectrum, 2011
You know when it's time to get a new car. Your odometer is far into six digits, perhaps the engine is burning lots of oil, or the transmission is growling. Fixing all that might well cost quite a bit more than your ancient vehicle is worth. But what about your microprocessor?
John Keane, Chris Kim
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You know when it's time to get a new car. Your odometer is far into six digits, perhaps the engine is burning lots of oil, or the transmission is growling. Fixing all that might well cost quite a bit more than your ancient vehicle is worth. But what about your microprocessor?
John Keane, Chris Kim
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