Results 101 to 110 of about 62,688 (226)
mprovement of Cache Memory Performance by Reducing Cache Miss Rate and Miss Penalty
مجلة جامعة الزيتونةCache is a small amount of memory which is part of the CPU which is physically closer to the CPU than RAM is the more cache there is the more data can be stored closer to the CPU.
Nagmden shtewi, Abdurrezagh Elmezughi
doaj
Journal of Low Power Electronics and Applications, 2017 The disparity between memory and CPU have been ameliorated by the introduction of Network-on-Chip-based Chip-Multiprocessors (NoC-based CMPS). However, power consumption continues to be an aggressive stumbling block halting the progress of technology ...
Emmanuel Ofori-Attah +2 more
doaj +1 more source
Simulation of L2 Cache Separation Impact in CPU Performance [PDF]
, 2015 Cache memory performance is very important in the overall performance of modern CPUs. One of the many techniques used to improve it is the split of on-chip cache memory in two separate Instruction and Data caches. The current CPU organizations usually have per core separate L1 caches and unified L2 caches.
openaire +1 more source
Analysis of cache for streaming tape drive [PDF]
A tape subsystem consists of a controller and a tape drive. Tapes are used for backup, data interchange, and software distribution. The backup operation is addressed.
Chinnaswamy, V.
core +1 more source
DeepPicar: A Low-cost Deep Neural Network-based Autonomous Car
, 2018 We present DeepPicar, a low-cost deep neural network based autonomous car platform. DeepPicar is a small scale replication of a real self-driving car called DAVE-2 by NVIDIA.
Bechtel, Michael G. +3 more
core +1 more source
Journal of Synchrotron Radiation, Volume 33, Issue 1, Page 106-114, January 2026.MAPI is a modular web‐based framework designed to unite legacy analysis code with heterogeneous backends (edge, on‐premises, high‐performance computing, cloud), dramatically accelerating data analysis workflows and offering a scalable flexible blueprint for modernizing synchrotron data analysis.In this paper, we introduce the Modular Adaptive ...
Aljoša Hafner +3 more
wiley +1 more source
6G Wireless Communications Enabled by the Blockchain: Privacy and Middleware Architecture
International Journal of Distributed Sensor Networks, Volume 2026, Issue 1, 2026.6G is transformational and brings revolutionary innovations in virtually all sectors, such as healthcare, autonomous systems, and manufacturing, through ultralow latency, massive connection, and far superior computing capabilities than any previous generation.
Moumita Chanda +4 more
wiley +1 more source
Research on Linux network packet buffer recycling toward multi-core processor
Tongxin xuebao, 2009 A lock-free algorithm for Linux packet buffer recycling on multi-core processor was proposed.Through making a model of Linux network packet forwarding, the principle of Linux packet buffer recycling was analyzed, and the main reason that the mechanism ...
YAO Qi +3 more
doaj +2 more sources
Enhancing Leakage Power in CPU Cache Using Inverted Architecture
International Journal of Modern Education and Computer Science, 2013 Power consumption is an increasingly pressing problem in modern processor design. Since the on-chip caches usually consume a significant amount of power so power and energy consumption parameters have become one of the most important design constraint. It is one of the most attractive targets for power reduction.
Bilal A. Shehada +2 more
openaire +1 more source
IEEE Access, 2018 It is challenging to achieve a consistent real-time (RT) response time in commodity virtual machine (VM) environments because they have longer and more complex network protocol stacks.
Oscar F. Garcia +2 more
doaj +1 more source