Results 101 to 110 of about 62,963 (220)

Research on Linux network packet buffer recycling toward multi-core processor

Tongxin xuebao, 2009
A lock-free algorithm for Linux packet buffer recycling on multi-core processor was proposed.Through making a model of Linux network packet forwarding, the principle of Linux packet buffer recycling was analyzed, and the main reason that the mechanism ...
YAO Qi, LIU Ji-qiang, HAN Zhen, SHEN Chang-xiang   +3 more
doaj   +2 more sources

Enhancing Leakage Power in CPU Cache Using Inverted Architecture

International Journal of Modern Education and Computer Science, 2013
Power consumption is an increasingly pressing problem in modern processor design. Since the on-chip caches usually consume a significant amount of power so power and energy consumption parameters have become one of the most important design constraint. It is one of the most attractive targets for power reduction.
Bilal A. Shehada, Ahmed M. Serdah, Aiman Abu Samra   +2 more
openaire   +1 more source

Large Pages, Large Leaks? Hugepage-Induced Side-Channels vs. Performance Improvements in Cryptographic Computations

Cryptography
Side-channel attacks leveraging microarchitectural components such as caches and translation lookaside buffers (TLBs) pose increasing risks to cryptographic and machine-learning workloads.
Xinyao Li, Akhilesh Tyagi
doaj   +1 more source

SmartNIC-Offloaded Worker Node for Storage-Compute Disaggregated Recommendation System [PDF]

Jisuanji gongcheng
Deep learning-based recommendation systems are commonly used to provide personalized recommendations. In a common storage-compute disaggregated inference architecture, the inference speed of the recommendation system is limited by the internode network ...
SHI Ruixin, YAN Ming, WU Jie
doaj   +1 more source

Tuning I/O Subsystem: A Key Component in RDBMS Performance Tuning [PDF]

Database Systems Journal, 2016
In a computer system, the fastest storage component is the CPU cache, followed by the system memory. I/O to disk is thousands of times slower than an access to memory. This fact is the key for why you try to make effective use of memory whenever possible
Hitesh Kumar SHARMA, Christalin Nelson. S, Sanjeev Kumar SINGH   +2 more
doaj  

Achieving Consistent Real-Time Latency at Scale in a Commodity Virtual Machine Environment Through Socket Outsourcing-Based Network Stacks

IEEE Access, 2018
It is challenging to achieve a consistent real-time (RT) response time in commodity virtual machine (VM) environments because they have longer and more complex network protocol stacks.
Oscar F. Garcia, Yasushi Shinjo, Calton Pu   +2 more
doaj   +1 more source

COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications

, 2023
Tommaso Marinelli, José Ignacio Gómez, Christian Tenllado, Francky Catthoor   +3 more
openalex   +2 more sources

Octant overlapping and angle-energy group expanded KBA parallelism of three-dimensional discrete ordinate method

Frontiers in Energy Research
IntroductionTo enhance the parallel efficiency of the conventional KBA spatial decomposition method, this study incorporates octant overlapping and angle-energy group expansion into the source iteration scheme for solving the discrete ordinate equations ...
Jian Guo, Jian Guo, Yang Zou, Yang Zou, Xuechao Zhao, Xuechao Zhao, Rui Yan, Rui Yan   +7 more
doaj   +1 more source

In-cache query co-processing on coupled CPU-GPU architectures [PDF]

, 2014
Jiong He, Shuhao Zhang, Bingsheng He
openalex   +1 more source

The problem of false splitting of CPU cache memory strings in multiprocessor systems [PDF]

, 2017
A.O. Kuzichkina, M.S. Kosyakov
openalex   +1 more source