Results 141 to 150 of about 263,258 (207)

An analysis of performance bottlenecks in MRI preprocessing. [PDF]

Gigascience
Dugré M, Chatelain Y, Glatard T.
europepmc   +1 more source

Aquila: Efficient In-Kernel System Call Telemetry for Cloud-Native Environments. [PDF]

Sensors (Basel)
Shin J, Kim J, Nam J.
europepmc   +1 more source

Quantum resilient security framework for privacy preserving AI in Apple MM1 on device architecture. [PDF]

Sci Rep
Umer N, Deng M, Zhang Y, Zhang M, Khan S.   +4 more
europepmc   +1 more source

AI powered multi feature fusion framework for retrieving images using color, texture and shape descriptors. [PDF]

Sci Rep
Naveen K, Parvathi RMS.
europepmc   +1 more source

Fast barcode calling based on <i>k</i>-mer distances. [PDF]

PNAS Nexus
Uphoff RC, Schüler S, Grosse I, Müller-Hannemann M.   +3 more
europepmc   +1 more source

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Line (Block) Size Choice for CPU Cache Memories

IEEE Transactions on Computers, 1987
The line (block) size of a cache memory is one of the parameters that most strongly affects cache performance. In this paper, we study the factors that relate to the selection of a cache line size. Our primary focus is on the cache miss ratio, but we also consider influences such as logic complexity, address tags, line crossers, I/O overruns, etc.
Alan Jay Smith
exaly   +3 more sources

Selective GPU caches to eliminate CPU-GPU HW cache coherence

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016
Cache coherence is ubiquitous in shared memory multiprocessors because it provides a simple, high performance memory abstraction to programmers. Recent work suggests extending hardware cache coherence between CPUs and GPUs to help support programming models with tightly coordinated sharing between CPU and GPU threads.
Neha Agarwal, David Nellans, Eiman Ebrahimi   +2 more
exaly   +3 more sources