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Proceedings 17th International Conference on Data Engineering, 2002
Since many existing techniques for exploiting CPU caches in the implementation of B-tree indexes have not been discussed in the literature, most of them are surveyed. Rather than providing a detailed performance evaluation for one or two of them on some specific contemporary hardware, the purpose is to survey and to make widely available this ...
G. Graefe, P.-A. Larson
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Since many existing techniques for exploiting CPU caches in the implementation of B-tree indexes have not been discussed in the literature, most of them are surveyed. Rather than providing a detailed performance evaluation for one or two of them on some specific contemporary hardware, the purpose is to survey and to make widely available this ...
G. Graefe, P.-A. Larson
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Selective GPU caches to eliminate CPU-GPU HW cache coherence
2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016Cache coherence is ubiquitous in shared memory multiprocessors because it provides a simple, high performance memory abstraction to programmers. Recent work suggests extending hardware cache coherence between CPUs and GPUs to help support programming models with tightly coordinated sharing between CPU and GPU threads.
Neha Agarwal +5 more
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Accelerating Concurrent Workloads with CPU Cache Partitioning
2018 IEEE 34th International Conference on Data Engineering (ICDE), 2018Modern microprocessors include a sophisticated hierarchy of caches to hide the latency of memory access and thereby speed up data processing. However, multiple cores within a processor usually share the same last-level cache. This can hurt performance, especially in concurrent workloads whenever a query suffers from cache pollution caused by another ...
Stefan Noll +3 more
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Functional implementation techniques for CPU cache memories
IEEE Transactions on Computers, 1999As the performance gap between processors and main memory continues to widen, increasingly aggressive implementations of cache memories are needed to bridge the gap. In this paper, we consider some of the issues that are involved in the implementation of highly optimized cache memories and survey the techniques that can be used to help achieve the ...
null Jih-Kwon Peir, W.W. Hsu, A.J. Smith
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CPU cache prefetching: Timing evaluation of hardware implementations
IEEE Transactions on Computers, 1998Prefetching into CPU caches has long been known to be effective in reducing the cache miss ratio, but known implementations of prefetching have been unsuccessful in improving CPU performance. The reasons for this are that prefetches interfere with normal cache operations by making cache address and data ports busy, the memory bus busy, the memory banks
J. Tse, A.J. Smith
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Dynamic CPU cache management under the loop model
Proceedings of Southcon '95, 2002Concerns cache designs using replacement strategies to provide the high performance required by fast CPUs. We propose a new replacement technique that uses some heuristic to detect loop structures in the reference patterns. Initially, the proposed technique uses the least recently used (LRU) strategy.
C. Jaouhar, I. Mahgoub, R. Hewett
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Accelerate Your Graphic Program with GPU/CPU Cache
2008 International Conference on Cyberworlds, 2008This paper discusses how to optimize the digital graphic program with cache system used in GPU/CPU architecture to gain more FPS. Firstly, we introduce the basic principle of cache system summarily; secondly, we discuss the three main organization and mapping technologies of cache system in detail, and then compare these three cache mapping solutions ...
Zhou Likun, Chen Dingfang
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Extending a CPU Cache for Efficient IPv6 Lookup
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), 2018Increasing throughput requirements for Internet routers and growing routing table sizes have emphasized the need for fast and scalable packet forwarding systems. This paper presents a hardware cache-based IPv6 lookup system. Our goal is to study how much performance can be achieved with a lookup system that is implemented by modifying a processor cache.
Benjamin Wolff +3 more
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Cache-efficient parallel eikonal solver for multicore CPUs
Computational Geosciences, 2018zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Alexandr A. Nikitin +2 more
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