Results 71 to 80 of about 263,258 (207)

To Cache or Not to Cache

Algorithms
Unlike conventional CPU caches, non-datapath caches, such as host-side flash caches which are extensively used as storage caches, have distinct requirements.
Steven Lyons, Raju Rangaswami
doaj   +1 more source

Data Rate Estimation for Wireless Core-to-Cache Communication in Multicore CPUs

Моделирование и анализ информационных систем, 2015
In this paper, a principal architecture of common purpose CPU and its main components are discussed, CPUs evolution is considered and drawbacks that prevent future CPU development are mentioned.
Maria S. Komar, V. Petrov, K. Borunova, D. Moltchanov, E. Koucheryavy   +4 more
doaj   +1 more source

Stochastic Pairwise MIS for Unbiased Large‐Kernel Reuse in Real‐Time

Computer Graphics Forum, EarlyView.
Abstract Spatiotemporal resampling methods such as ReSTIR decrease noise in Monte Carlo rendering of dynamic content by reusing paths across frames and pixels. Standard ReSTIR reuses spatially from a small number of randomly selected neighbors. This reuse suffers when few neighbors contain contributing samples, reducing quality toward that of the ...
Trevor Hedstrom, Markus Kettunen, Daqi Lin, Chris Wyman, Tzu‐Mao Li   +4 more
wiley   +1 more source

Register‐Efficient Linear‐Time Evaluation in the Bernstein Basis

Computer Graphics Forum, EarlyView.
Abstract We investigate the evaluation of points and derivatives of Bézier curves and surfaces on modern architectures, focusing on performance and guided by numerical error bounds. While the de Casteljau algorithm remains the reference for numerical robustness, its linear working‐set size imposes substantial register pressure on GPUs.
Gábor Valasek, Anna Lili Horváth
wiley   +1 more source

NAADF: Globally Illuminated Voxel Worlds Accelerated with Nested Axis‐Aligned Distance Fields

Computer Graphics Forum, EarlyView.
Abstract Achieving realistic rendering of 3D scenes in real time using path tracing is challenging due to the high sample count required, with ray tracing as the bottleneck. Focusing on voxels as a geometry representation offers significant opportunities for optimizations, especially for tracing the rays, but also for computing the samples.
A. Ulschmid, M. Ott, J. Macho, M. Wimmer, S. Ohrhallinger   +4 more
wiley   +1 more source

Reproducibility assessment of Dextrusion: A deep learning pipeline for detecting epithelial cell extrusion events

Journal of Microscopy, EarlyView.
Abstract Reproducibility is essential for scientific software but can be hindered by technical and maintenance challenges. As part of the Global Bioimage Analyst Society reproducibility initiative, we evaluated Dextrusion, a deep learning pipeline for detecting epithelial cell extrusion events published by Villars et al.
Nicholas D Condon, Jian Xiong Wang, Alessandro A Felder   +2 more
wiley   +1 more source

mprovement of Cache Memory Performance by Reducing Cache Miss Rate and Miss Penalty

مجلة جامعة الزيتونة
Cache is a small amount of memory which is part of the CPU which is physically closer to the CPU than RAM is the more cache there is the more data can be stored closer to the CPU.
Nagmden shtewi, Abdurrezagh Elmezughi
doaj  

Perspectives On Machine Learning Inference Serving in Real‐World Settings

Software: Practice and Experience, Volume 56, Issue 6, Page 734-757, June 2026.
ABSTRACT Introduction As machine learning (ML)‐enabled systems become increasingly prevalent across industries, the engineering challenges of deploying and maintaining them in production have emerged as critical. The existing engineering knowledge base often derives from conceptual frameworks or case studies conducted by large technology companies ...
Dennis Muiruri, Lucy Ellen Lwakatare, Jukka K. Nurminen, Tommi Mikkonen   +3 more
wiley   +1 more source

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

Journal of Low Power Electronics and Applications, 2017
The disparity between memory and CPU have been ameliorated by the introduction of Network-on-Chip-based Chip-Multiprocessors (NoC-based CMPS). However, power consumption continues to be an aggressive stumbling block halting the progress of technology ...
Emmanuel Ofori-Attah, Washington Bhebhe, Michael Opoku Agyeman   +2 more
doaj   +1 more source

Oxide Ceramics Large‐Scale Integration Devices to Mitigate Global Extreme Weather Due to Computers in the AI Era

International Journal of Ceramic Engineering &Science, Volume 8, Issue 3, May 2026.
Crystal IO FETs feature (1) extremely low off current and (2) high on current. For ultralow‐power consumption, we are aiming at replacing conventional memories by crystal IO‐based memories and ultralow‐power ALUs using AiMC FETs in the subthreshold regime. This report will introduce the trend of these technologies.
Shunpei Yamazaki, Tatsuya Onuki, Satoru Saito, Kazuki Tsuda, Hiromichi Godo, Takanori Matsuzaki, Koji Kusunoki, Yuto Yakubo, Hidekazu Miyairi, Ryota Hodo, Yasuhiro Jinbo, Fumito Isaka, Yuji Egi, Yoshinori Ando, Motomu Kurata, Tsutomu Murakawa, Takashi Shingu, Ryosuke Motoyoshi, Yosuke Tsukamoto, Yukinori Shima, Masami Jincho, Yasutaka Nakazawa, Masahiro Watanabe, Kayo Kumakura, Masataka Nakada, Ami Sato, Nobuharu Ohsawa, Kenichi Okazaki   +27 more
wiley   +1 more source