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Parallel crc realization

IEEE Transactions on Computers, 2003
This paper presents a theoretical result in the context of realizing high-speed hardware for parallel CRC checksums. Starting from the serial implementation widely reported in the literature, we have identified a recursive formula from which our parallel implementation is derived.
G. CAMPOBELLO, G. PATANE', RUSSO, Marco
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CRC

Proceedings of the Tenth ACM International Workshop on Wireless Network Testbeds, Experimental Evaluation, and Characterization, 2016
The validation of wireless communications research, whether it is focused on PHY, MAC or higher layers, can be done in several ways, each with its limitations. Simulations tend to be simplified. Equipping wireless labs requires funding and time. Remotely accessible testbeds present a good option to validate research.
Samer S. Hanna   +5 more
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Parallel CRC generation

IEEE Micro, 1990
Theoretical aspects of encoding cyclic redundant codes (CRCs) are reviewed. A method of designing hardware parallel encoders for CRCs that is based on digital system theory and z-transforms is presented. It allows designers to derive the logic equations of the parallel encoder circuit for any generator polynomial.
ALBERTENGO, GUIDO, SISTO, Riccardo
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Fast CRC calculation

Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93, 2002
The integrity of messages in data communications is always ensured by the addition, at the end of the message, of a frame check sequence (FCS) traveling with the message itself so it can be checked at far end for proper transmission. A cyclic redundancy code (CRC) is employed to generate FCS at one end and check the entire received message (data plus ...
R.J. Glaise, X. Jacquart
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