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Parallel crc realization

IEEE Transactions on Computers, 2003
This paper presents a theoretical result in the context of realizing high-speed hardware for parallel CRC checksums. Starting from the serial implementation widely reported in the literature, we have identified a recursive formula from which our parallel implementation is derived.
G. CAMPOBELLO, G. PATANE', RUSSO, Marco
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Parallel CRC generation

IEEE Micro, 1990
Theoretical aspects of encoding cyclic redundant codes (CRCs) are reviewed. A method of designing hardware parallel encoders for CRCs that is based on digital system theory and z-transforms is presented. It allows designers to derive the logic equations of the parallel encoder circuit for any generator polynomial.
ALBERTENGO, GUIDO, SISTO, Riccardo
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