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Triplex: an Efficient and One-Pass Leakage-Resistant Mode of Operation
Transactions on Cryptographic Hardware and Embedded Systems, 2022 This paper introduces and analyzes Triplex, a leakage-resistant mode of operation based on Tweakable Block Ciphers (TBCs) with 2n-bit tweaks. Triplex enjoys beyond-birthday ciphertext integrity in the presence of encryption and decryption leakage in a ...
Yaobin Shen +4 more
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Exploring Crypto-Physical Dark Matter and Learning with Physical Rounding
Transactions on Cryptographic Hardware and Embedded Systems, 2020 State-of-the-art re-keying schemes can be viewed as a tradeoff between efficient but heuristic solutions based on binary field multiplications, that are only secure if implemented with a sufficient amount of noise, and formal but more expensive solutions
Sébastien Duval +3 more
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Improved Leakage-Resistant Authenticated Encryption based on Hardware AES Coprocessors
Transactions on Cryptographic Hardware and Embedded Systems, 2021 We revisit Unterstein et al.’s leakage-resilient authenticated encryption scheme from CHES 2020. Its main goal is to enable secure software updates by leveraging unprotected (e.g., AES, SHA256) coprocessors available on low-end microcontrollers.
Olivier Bronchain +3 more
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When Bad News Become Good News
Transactions on Cryptographic Hardware and Embedded Systems, 2022 Hard physical learning problems have been introduced as an alternative option to implement cryptosystems based on hard learning problems. Their high-level idea is to use inexact computing to generate erroneous computations directly, rather than to first
Davide Bellizia +4 more
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Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype
Transactions on Cryptographic Hardware and Embedded Systems, 2021 Hard learning problems are important building blocks for the design of various cryptographic functionalities such as authentication protocols and post-quantum public key encryption.
Davide Bellizia +6 more
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Information Bounds and Convergence Rates for Side-Channel Security Evaluators
Transactions on Cryptographic Hardware and Embedded Systems, 2023 Current side-channel evaluation methodologies exhibit a gap between inefficient tools offering strong theoretical guarantees and efficient tools only offering heuristic (sometimes case-specific) guarantees.
Loïc Masure +3 more
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Bitslicing Arithmetic/Boolean Masking Conversions for Fun and Profit
Transactions on Cryptographic Hardware and Embedded Systems, 2022 The performance of higher-order masked implementations of lattice-based based key encapsulation mechanisms (KEM) is currently limited by the costly conversions between arithmetic and Boolean masking.
Olivier Bronchain, Gaëtan Cassiers
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Transactions on Cryptographic Hardware and Embedded Systems, 2021 There exists many masking schemes to protect implementations of cryptographic operations against side-channel attacks. It is common practice to analyze the security of these schemes in the probing model, or its variant which takes into account physical ...
Gaëtan Cassiers +1 more
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Efficient and Private Computations with Code-Based Masking
Transactions on Cryptographic Hardware and Embedded Systems, 2020 Code-based masking is a very general type of masking scheme that covers Boolean masking, inner product masking, direct sum masking, and so on. The merits of the generalization are twofold.
Weijia Wang +3 more
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Prime-Field Masking in Hardware and its Soundness against Low-Noise SCA Attacks
Transactions on Cryptographic Hardware and Embedded Systems, 2023 A recent study suggests that arithmetic masking in prime fields leads to stronger security guarantees against passive physical adversaries than Boolean masking.
Gaëtan Cassiers +4 more
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