Results 91 to 100 of about 3,906 (206)
Selecting A Cyclic Redundancy Check (CRC) Generator Polynomial for CEH (CRC Extension Header). [PDF]
, 2009 Computation and regeneration of CRC code in each router may cause slower IPv6 packet ...
Budiarto, Rahmat +2 more
core
Generalized Parallel CRC Computation on FPGA
, 2015 The cyclic redundancy check (CRC) is a popular error detection code (EDC) used in many digital transmission and storage protocols. Most existing digit-serial hardware CRC computation architectures are based on one of the two well-known bit-serial CRC ...
Mozaffari Kermani, Mehran +3 more
core +1 more source
Jurnal Jaringan TelekomunikasiWireless sensor networks (WSN) play a vital role in collecting distributed data for various applications, including environmental monitoring and smart city systems. Although WSNs promise great potential, communication challenges are a major obstacle that
Khomsanes Adzimatunnisa +2 more
doaj +1 more source
Penerapan CRC 32 dalam Pengecekan Kesalahan pada Pengiriman File
, 2019 Error often occurs in sending data, where the error is caused by interference at the physical level, namely interference with the transmission line media, such as interference with electromagnetic radiation, lightning or interference caused by noise ...
Pristiwanto
core
Journal of Marine Science and EngineeringAddressing the challenges of high decoding latency, reduced spectral efficiency, and substantial storage requirements in a Cyclic Redundancy Check (CRC)Aided Successive Cancellation List (CA-SCL) polar decoder, this paper proposes a chaotic phase ...
Yuan Sun +3 more
doaj +1 more source
Single Bit Error Correction Implementation in CRC-16 on FPGA [PDF]
, 2004 Framing protocols employ cyclic redundancy check (CRC) to detect errors incurred during transmission. Generally whole frame is protected using CRC and upon detection of error, retransmission is requested. But certain protocols demand for single bit error
Bergmann, Neil, Shukla, Sunil
core
Plenary Abstracts Session & Oral Presentations
HemaSphere, Volume 10, Issue S1, June 2026.
wiley +1 more source
High Speed Low Power Cyclic Redundancy Check-32 using FPGA
, 2019 Cyclic Redundancy Check (CRC) is a method used for error detection technique and data integrity. CRC take a block of a message‟s bits and divide it by a binary number called polynomial, the result of this division is the checksum that will be added to ...
Abdulnabi, Mohamed Abdulnabi
core