Results 121 to 130 of about 737 (169)

Implementation of Table-Based Cyclic Redundancy Check (CRC-32) for Gigabit Ethernet Applications

2023 4th International Conference for Emerging Technology (INCET), 2023
P Kishore
exaly   +2 more sources

Design of Cyclic Redundancy Check (CRC) Code Generator Circuit in Quantum Dot Cellular Automata (QCA) for Communication

2023 26th International Conference on Computer and Information Technology (ICCIT), 2023
Mohammad Ishtiaque Khan, Muhammad Mostafa Amir Faisal   +1 more
exaly   +2 more sources

Cyclic Redundancy Check (CRC)

2009
exaly   +2 more sources

Cyclic redundancy check (CRC) program listing

2003
exaly   +2 more sources

A self-timed cyclic redundancy check (CRC) in VLSI

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg, 1999
A self-timed approach to implement a cyclic redundancy check (CRC) for the application of telecommunications is described. The approach is oriented toward multiple channel communications. The paper presents a new scheme to handle an asynchronous feedback to implement the CRC engine.
S.Henry Li, Charles A. Zukowski
openaire   +1 more source

Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010
A proven approach to increase performance of general-purpose processors is to add hardware accelerators. In its basic configuration, the FlexCore processor has a limited set of datapath units. But thanks to a flexible datapath interconnect and a wide control word, the FlexCore datapath is explicitly designed to support integration of special units that,
Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors   +2 more
openaire   +1 more source

Interleaved cyclic redundancy check (CRC) code

The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003, 2004
In this paper, we investigate interleaved cyclic redundancy check (CRC) code. The interleaved CRC can be obtained by merging independent small message blocks into one large block (merged interleaving) or by dividing the original message block into independent small sub blocks (divided interleaving) and then by alternatively dividing the resulting ...
null Jun Jin Kong, K.K. Parhi
openaire   +1 more source

Pipelined Cyclic Redundancy Check (CRC) Calculation

2007 16th International Conference on Computer Communications and Networks, 2007
Traditional methods to calculate CRC suffer from diminishing returns. Doubling the data width doesn't double the maximum data throughput, the worst case timing path becomes slower. Feedback in the traditional implementation makes pipelining problematic. However, the on chip data width used for high throughput protocols is constantly increasing.
openaire   +1 more source

A symbol based algorithm for hardware implementation of cyclic redundancy check (CRC)

Proceedings VHDL International Users' Forum. Fall Conference, 2002
Describes a symbolic simulation-based algorithm to derive optimized Boolean equations for a parameterizable data width CRC generator/checker. The equations are then used to implement a data flow representation of the CRC circuit in VHDL. The VHDL description is subsequently synthesized to gates.
R. Nair, G. Ryan, F. Farzaneh
openaire   +1 more source

Embedding a secondary communication channel transparently within a cyclic redundancy check (CRC)

IBM Journal of Research and Development, 2001
Techniques are proposed for transparently recapturing part of the capacity of a cyclic redundancy check (CRC) and using the recaptured capacity to carry a secondary communication channel. To do this, a transmitter induces CRC violations in outbound packets of a primary channel according to a set of error templates that are known to both the transmitter
openaire   +1 more source