Results 261 to 270 of about 256,454 (322)

A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET

IEEE Journal of Solid-State Circuits, 2022
This article presents analysis, design details, and measurement result of a 224-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter (TX) consisting of a 7-bit voltage digital-to-analog converter (DAC) driver, digital 8-tap feed-forward ...
Jihwan Kim, S. Kundu, A. Balankutty, Matthew Beach, Bong Chan Kim, Stephen T. Kim, Yutao Liu, S. Murthy, Priya Wali, Kai Yu, Hyung Seok Kim, Chuanchang Liu, Dongseok Shin, Ariel Cohen, Yoav Segal, Yongping Fan, P. Li, F. O’Mahony   +17 more
semanticscholar   +1 more source

Analysis of Uplink Cell-Free Massive MIMO System With Mixed-ADC/DAC Receiver

IEEE Systems Journal, 2021
A generalized uplink cell-free massive multi-input multi-output (MIMO) system assuming access points (APs) are paired with mixed-resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) is investigated in this article ...
Yao Zhang, Yulun Cheng, Meng Zhou, Longxiang Yang, Hongbo Zhu   +4 more
semanticscholar   +1 more source

A 134-μW 99.4-dB SNDR Audio Continuous-Time Delta-Sigma Modulator With Chopped Negative-R and Tri-Level FIR-DAC

IEEE Journal of Solid-State Circuits, 2020
This article presents a low-power audio continuous-time delta-sigma modulator (CTDSM) that employs a chopped negative-R and a tri-level finite impulse-response (FIR) DAC.
Moonhyung Jang, Changuk Lee, Youngcheol Chae   +2 more
semanticscholar   +1 more source

Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020
This work presents a unified weak physical unclonable function (PUF) and a true random number generator (TRNG) based on the current-steering digital-to-analog converter (DAC) and ring voltage-controlled oscillator (VCO).
Mohammadhadi Danesh, Aishwarya Bahudhanam Venkatasubramaniyan, Gaurav Kapoor, Naveen Ramesh, Sudarsan Sadasivuni, S. T. Chandrasekaran, A. Sanyal   +6 more
semanticscholar   +1 more source

Bias Voltage DAC Operating at Cryogenic Temperatures for Solid-State Qubit Applications

IEEE Solid-State Circuits Letters, 2020
A scalable eight channel DAC designed in a TSMC 65-nm CMOS technology for generation of solid-state quantum bit (qubit) bias voltages is presented. Measurement results of the DAC and some additional auxiliary components like an on-chip amplifier and ...
P. Vliex, C. Degenhardt, C. Grewing, A. Kruth, D. Nielinger, S. van Waasen, S. Heinen   +6 more
semanticscholar   +1 more source

9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s

IEEE International Solid-State Circuits Conference, 2020
High-precision current-measurement front-ends are widely used in various applications, such as photoplethysmography (PPG) recording by biomedical sensors and molecular-concentration detection by electrochemical sensors.
Su-Hao Wu, Yun-Shiang Shu, A. C. Chiou, Wei-Hsiang Huang, Zhi-Xin Chen, Hung-Yi Hsieh   +5 more
semanticscholar   +1 more source

Mixed-ADC/DAC Multipair Massive MIMO Relaying Systems: Performance Analysis and Power Optimization

IEEE Transactions on Communications, 2018
High power consumption and expensive hardware are two bottlenecks for practical massive multiple-input multiple-output (mMIMO) systems. One promising solution is to employ low-resolution analog-to-digital converters (ADCs) and digital-to-analog ...
Jiayi Zhang, L. Dai, Ziyan He, B. Ai, O. Dobre   +4 more
semanticscholar   +1 more source

DACS

Proceedings of the Symposium on Applied Computing, 2017
Virtual machines are used in various fields to increase the resource utilization. In a virtual machine monitor, I/O requests are the most frequent tasks for virtual machines. However, a virtual machine monitor cannot guarantee I/O responsiveness when multiple tasks are being performed on virtual machines.
Myungjoon Shon, Kisu Kim, Hansol Lee, Sung Y. Shin, Jiman Hong   +4 more
openaire   +1 more source

A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC

IEEE Journal of Solid-State Circuits, 2018
This paper presents an 11-bit ultralow voltage energy efficient successive approximation register (SAR) analog-to-digital converter (ADC). With the proposed semi-resting (SR) digital-to-analog convertor (DAC) switching scheme, this paper consumes only 6%–
Sung-En Hsieh, C. Hsieh
semanticscholar   +1 more source

A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS

IEEE Transactions on Circuits and Systems - II - Express Briefs, 2018
This brief presents a high-speed successive approximation register analog-to-digital converter (ADC) with nonbinary searching technique. By inserting redundancy in the first five decision steps, the digital-to-analog converter (DAC) settling errors can ...
Dengquan Li, Zhangming Zhu, R. Ding, Yintang Yang   +3 more
semanticscholar   +1 more source