Results 51 to 60 of about 1,316 (216)
Data Parallel Address Architecture [PDF]
Data parallel memory systems must maintain a large number of outstanding memory references to fully use increasing DRAM bandwidth in the presence of increasing latency. At the same time, the throughput of modern DRAMs is very sensitive to access pattern's due to the time required to precharge and activate banks and to switch between read and write ...
Jung Ho Ahn, William J. Dally
openaire +2 more sources
Performance–Complexity Trade‐Offs in Battery Lifetime Prediction with Task‐Aware Transformers
FAST‐BatPro integrates convolutional feature extraction, flash Attention, and sparse attention for efficient battery lifetime prediction. Using limited early‐cycle data across multiple chemistries and operating conditions, it achieves robust accuracy while reducing inference latency, computational cost, and energy consumption.
Jingyuan Zhao +9 more
wiley +1 more source
Image classification using machine learning techniques is crucial in fields such as medicine, ecology, and agriculture, where large datasets of images need to be processed efficiently.
Леся МОЧУРАД +2 more
doaj +1 more source
Exploiting the parallelism in multiprocessor systems is a major challenge in modern computer science. Multicore programming demands a change in the way we design and use fundamental data structures.
Damian Dechev +2 more
doaj +1 more source
Neuromorphic Near‐Sensor and In‐Sensor Computing Enabled by Next‐Generation Material‐Based Sensors
This Review presents a structural framework that classifies neuromorphic sensing into near‐sensor and in‐sensor architectures, clarifying physical coupling between sensing and computation. The framework connects neural and synaptic device functions with recent advances in optical, mechanical, and chemical sensing, compares energy consumption and ...
Su Yeon Jung +7 more
wiley +1 more source
Modern embedded systems such as autonomous vehicles and robotics increasingly rely on high-performance computing to satisfy real-time and data-intensive demands.
Shanwen Wu, Qi Li, Masato Edahiro
doaj +1 more source
Exploring Various Levels of Parallelism in High-Performance CRC Algorithms
Modern processors have increased the capabilities of instruction-level parallelism (ILP) and thread-level parallelism (TLP). These resources, however, typically exhibit poor utilization on conventional cyclic redundancy check (CRC) algorithms.
Mucong Chi, Dazhong He, Jun Liu
doaj +1 more source
Photonic‐Enabled Energy‐Efficient Transparent Neuromorphic Computing Devices: A Review
Transparent photonic neuromorphic computing devices merge optics and brain‐inspired computing to overcome von Neumann bottlenecks with ultrafast, low‐energy processing. By exploiting transparent oxides, 2D materials, phase‐change materials, and hybrid heterostructures, these platforms enable photonic synapses, memory, and logic for see‐through edge ...
Shuvaraj Ghosh +8 more
wiley +1 more source
THE PERFORMANCE OF CONVOLUTIONAL NEURAL NETWORKS USING AN ACCELERATOR
The effectiveness of convolutional neural networks (CNNs) has been demonstrated across various fields, including computer vision, natural language processing, medical imaging, and autonomous systems.
Tymur ISAIEV, Tetiana KYSIL
doaj +1 more source
A nanoporous SiO2 memristor enabling reconfigurable volatile and non‐volatile switching within a single device is demonstrated. The dual‐mode functionality supports both physical reservoir dynamics and synaptic weight storage, allowing unified hardware implementation of reservoir computing for temporal information processing, including image and ...
Bohao Ding +5 more
wiley +1 more source

