Results 251 to 260 of about 366,258 (347)
Never say die [integrated circuit tests]
IEE Review, 2005 Perfection is an illusion - even integrated circuits that pass all tests at birth can lose their abilities in old age. New research is looking at ways of stopping so many chips ending up on the scrap heap. The paper looks at whether escalating gate counts on integrated circuits will make the fault-free chip an unrealisable ideal, and what this would ...
S. Baines
semanticscholar +3 more sources
Scheduling Integrated Circuit Assembly Operations on Die Bonder
IEEE Transactions on Electronics Packaging Manufacturing, 2007 Solving the integrated circuit (IC) assembly scheduling problem (ICASP) is a very challenging task in the IC manufacturing industry. In the IC assembly factories, the jobs are assigned processing priorities and are clustered by their product types, which must be processed on groups of identical parallel machines.
W. L. Pearn, S. H. Chung, Olivier Lai
semanticscholar +3 more sources
Horizontal Die Cracking as a Yield and Reliability Problem in Integrated Circuit Devices
IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1987 The problem of horizontal silicon die cracking, which can occur in CERDIP packages with glass as a die bonding material, is addressed. This fracture mode has been attributed to the combined effects of mechanical and thermal stresses. The mechanism of the fracture will be proposed and related to both the die edge condition and the die attach process ...
Y.M. Kasem, L.G. Feinstein
semanticscholar +3 more sources
Integrated Circuit Die Level Yield Prediction Using Deep Learning
2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2022 Given the integrated circuits (IC) production scale, the amount of process control monitoring (PCM) data enable to develop an efficient algorithm for IC yield prediction at the die-level.
Petr Lenhard +2 more
semanticscholar +3 more sources
18th International Reliability Physics Symposium, 1980 A technique (the capacitance-ratio test) is described for assessing the water content of hermetic packages containing an integrated circuit die. It is based on a theoretical analysis which shows that the frequency dependence of the capacitance between a selected pair of IC metallisation tracks can be used to derive the moisture induced component of ...
R.P. Merrett, Sung-Hun Sim, J P Bryant
semanticscholar +3 more sources
Thermal characteristics of multi-die, three-dimensional integrated circuits with unequally sized die
2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2010 Three-dimensional integrated circuits (3D ICs) technology involves significant thermal management challenges due to the overlap of heat dissipation from several die. One particular problem is related to the thermal management of a multi-die stack with unequally-sized die. This is an important problem since several 3D IC process integration technologies
Ankur Jain
openalex +2 more sources
Detecting a trojan die in 3D stacked integrated circuits
2017 IEEE North Atlantic Test Workshop (NATW), 2017 While 3D integrated circuits provide many security advantages, one disadvantage is the insertion of a Trojan die into the stack. In this paper, we explore a technique to detect an extra die through delay analysis.
Soha Alhelaly +5 more
openalex +2 more sources
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
2018 IEEE International Test Conference (ITC), 2018 Multi-die stacked ICs are getting increasing traction in the market, fueled by innovations in wafer processing technologies (e.g., vertical inter-die and intra-die connections), stack assembly, and advanced packaging approaches (e.g., wafer-level packaging).
Erik Jan Marinissen +5 more
openalex +2 more sources
Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits
Microelectronics Reliability, 2017 Abstract In three-dimensional integrated circuits (3DICs) aggressive wafer-thinning can lead to large thermal gradients, including spikes in individual device temperatures. In a non-thinned circuit, the large bulk silicon wafer on which devices are built works as a very good thermal conductor, enabling heat to diffuse laterally.
Samson Melamed +5 more
openalex +2 more sources
Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits
2011 14th Euromicro Conference on Digital System Design, 2011 Shorter interconnects and higher integration are among the benefits that 3D die-stacking is expected to bring to future integrated circuits. However, when stacking power-dissipating dies one on top of the other, the total power density increases accordingly. As a result, temperatures in 3DICs are exacerbated.
Hadrien A. Clarke, Kazuaki Murakami
openalex +2 more sources