Results 211 to 220 of about 20,242 (263)
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2015
The last chapters present design details of ADCs in detail with the focus on SAR ADCs in the Chaps. 2 and 3 and delta-sigma ADCs in the Chaps. 4 and 5. Chapter 6 discusses the test and verification of ADCs as well as the external circuitry around the ADC in an application.
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The last chapters present design details of ADCs in detail with the focus on SAR ADCs in the Chaps. 2 and 3 and delta-sigma ADCs in the Chaps. 4 and 5. Chapter 6 discusses the test and verification of ADCs as well as the external circuitry around the ADC in an application.
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The evolution of digital to analog converter
2016 International Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEES), 2016In the past few decades there have been many developments in the design methodology of DAC to meet the stringent performance requirements of their endless applications. These design strategies can be categorized into several classifications. Based on the literature review the history of the evolution, advantages and limitation of each method can be ...
L. F. Rahman +3 more
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2013
In this chapter, the concept and performance specifications of digital-to-analog converters (DACs) are reviewed. Different DAC architectures and physical implementations are introduced. Recently published state-of-the-art DACs are summarized to show the performance limitations.
Yongjian Tang +2 more
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In this chapter, the concept and performance specifications of digital-to-analog converters (DACs) are reviewed. Different DAC architectures and physical implementations are introduced. Recently published state-of-the-art DACs are summarized to show the performance limitations.
Yongjian Tang +2 more
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An SFQ digital to analog converter
IEEE Transactions on Appiled Superconductivity, 1997We have developed and demonstrated a digital to analog converter DAC which uses an SFQ counter to precisely divide an input reference oscillator to produce a set of binary frequencies/voltages. The binary input gates the output SFQ pulses of the counter flip flops to a passive summing network, producing an analog output current. The DAC is asynchronous
R.D. Sandell, B.J. Dalrymple, A.D. Smith
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A charge transfer multiplying digital-to-analog converter
1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1976A new charge-transfer multiplying digital-to-analog converter employs an array of binary-weighted MOS capacitors and MOS transistors as its only elements. It can be fabricated on the same chip and by the same process as most charge-coupled devices and bucket-brigade devices, and provides two- or four-quadrant multiplication.
J.F. Albarran, D.A. Hodges
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A digital-to-analog converter for a cortical microelectrode stimulator
2012 IEEE International Symposium on Circuits and Systems, 2012This paper describes an integrated digital-to-analog converter (DAC) for a intra-cortical microelectrode stimulator. The circuit has a special feature that consists on charging and discharging the same current to prevent electric charge accumulation that might harm the brain. The DAC has 5 bits of resolution supplying a maximum current of 100 µA to one
Miguel A. Martins +3 more
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Quadrature Mismatch Shaping for Digital-to-Analog Converters
IEEE Transactions on Circuits and Systems I: Regular Papers, 2006Quadrature sigma-delta analog-to-digital converters require a feedback path for both the I and the Q parts of the complex feedback signal. If two separate multibit feedback digital-to-analog converters (DACs) are used, mismatch among the unit DAC elements leads to additional mismatch noise in the output spectrum as well as an I/Q imbalance.
Stijn Reekmans +3 more
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An INL Yield Model of the Digital-to-Analog Converter
IEEE Transactions on Circuits and Systems I: Regular Papers, 2013The integral nonlinearity (INL) yield of any arbitrarily segmented digital-to-analog converter (DAC) has not been accurately modeled and requires long simulation time. This paper proposes an intuitive formulation of the INL yield that leads to a simple and accurate relation between the variation of the unit source element and the DAC yield with only a ...
Henry Park, Chih-Kong Ken Yang
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Analog-to-Digital Converters: Digitizing the Analog World
Proceedings of the IEEE, 2008Challenges in analog-to-digital (A/D) conversion for future scaled complementary metal-oxide-semiconductor (CMOS) technologies are investigated. The analysis of a figure of merit (FOM) that accounts for energy per conversion step indicates that op-amps are one of the most significant performance bottlenecks.
Hae-Seung Lee, Charles G. Sodini
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Modelling of CMOS digital-to-analog converters for telecommunication
ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187), 1999This paper gives an overview of some of the effects caused by circuit mismatch and parasitics in binary weighted digital-to-analog converters (DACs), and, as a special case, a current-steering CMOS converter. Matlab is used as a behavior-level simulator. In telecommunications applications, the frequency-domain parameters are of the greatest importance.
J.J. Wikner, null Nianxiong Tan
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