Results 71 to 80 of about 35,258,878 (189)
, 2019 V předložené práci jsou popsány procesy vedoucí k analogovému návrhu LDO regulátoru s PMOS výkonovým prvkem v technologii BCD8 společnosti STMicroelektronics.
Martin Kaňok
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An Ultra Low-Power LDO for MCU in Standby Mode
, 2017 设计了一种应用于MCU待机模式的超低功耗低压差线性稳压电路(LDO)。采用较少的MOS管以及简单的结构,只需提供一个15n A的偏置电流,可自产生偏置电压,无需带隙基准(Bandgap reference)电路提供基准电压。针对与主LDO协同工作的情况设计了输出级,能有效避免LDO同时工作引起的电源电压波动。在MCU的待机模式下,可以给上电复位(POR)、唤醒电路(Wakeup)、低功耗振荡器(LPOSC)、数据保持(Data retention)电路提供电源电压。该电路采用TSMC 0 ...
刘铁锋, 张超, 张志鹏
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This article presents a fully synthesizable, finegrained, distributed all-digital 6x6 LDO fabric in which modular micro-LDO regulator units are freely linkable-no centralized controller is required-enabling seamless scaling to arbitrarily large SoC power
Lee, Yong-Jin +2 more
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A 3-stage Cap-Less LDO Regulator for DCO with Phase Noise Reduction Technique
, 2022 This paper presents a 3-stage Cap-Less(Capacitor-Less) LDO(Low Drop Out) regulator for DCO(Digital Controlled Oscillator) with phase noise reduction technology.
il jeong
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High PSRR linear low dropout regulator (LDO)
, 2014 In many on-chip systems, low dropout regulators (LDO) are used to provide a clean power supply to various blocks, while taking in noisy supply from more efficient DC-DC converters.
Tan, Jing Yuan
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, 2018 本发明提供了一种LDO电路，所述LDO电路包括基准源、差分放大器、LDO输出级。所述基准源提供一个基准电压和一个基准电流偏置电压；所述差分放大器的第一输入端连接基准源输出的基准电压，第二输入端连接所述LDO的输出电压，所述差分放大器的输出端连接到所述LDO输出功率管的栅极。差分放大器和LDO输出级形成闭合回路，使输出电压稳定到基准电压。本发明的LDO输出级包括一个尾电流源NM6，可以减小输出电压的波动。LDO电路结构简单，对工艺要求较低 ...
董策 +4 more
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A comparative analysis on binary and multiple-unary weighted power stage design for digital LDO
, 2017 An analytical study of designing power stage for the emerging digital LDO is presented in this paper. Two widely adopted sizing options are discussed, namely binary and multiple-unary weighted power stage sizing.
Lu, Yasu, Yang, Fan, Mok, Philip K.T.
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An Analog-Assisted Digital LDO With Single Subthreshold Output pMOS Achieving 1.44-fs FOM
This letter describes an analog-assisted digital LDO that cascades a conventional digital LDO structure with a single, large output pMOS biased in subthreshold to enable fast response to output voltage droop.
Xu, Li +3 more
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Design of capacitorless LDO with compensation circuits
, 2009 This project proposes two solutions to the present bulky external capacitor low-dropout voltage regulators (LDO). The large output capacitor is reduced allowing for greater power system integration for system-on-chip (SoC) application, while the LDO ...
Xiong, Yuanting.
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Design of a linear low drop out (LDO) voltage regulator
, 2010 The drastic increase in the use of battery powered portable devices has required electronic devices to be able to work in low voltage environment. Power management systems are then becoming more crucial in those devices.
Lawrence, Jennifer.
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