Results 71 to 77 of about 79 (77)

A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients

2011
Maged Ghoneima, Yehea Ismail
exaly  

A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition

IEEE Journal of Solid-State Circuits, 2006
Michael H Perrott
exaly  

A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter

2012
Maged Ghoneima, Yehea Ismail
exaly  

Digital Filter and Forward Full Duplex (FF-FD) Relay: Exploiting the Loop Back Signal

IEEE Transactions on Wireless Communications, 2018
Shijian Gao, Xiang Cheng, Liuqing Yang   +2 more
exaly  

An Adaptive Digital Loop Filter for Fast-Locking TDC-Based ADPLL

Kaiqiang Qin, Bharatha Kumar Thangarasu, Kaixue Ma   +2 more
exaly  

A digital loop filter for a Phase Locked Loop

2011
exaly  

An Alternate Method to Design Digital Loop Filter of All Digital PLL using Zero Order Hold

Mohd Ziauddin Jahangir
exaly