Results 11 to 20 of about 1,399,763 (373)
MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning [PDF]
IEEE Transactions on Biomedical Circuits and Systems, 2019 Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip
C. Frenkel, J. Legat, D. Bol
semanticscholar +1 more source
A Survey on Application Specific Processor Architectures for Digital Hearing Aids [PDF]
Journal of Signal Processing Systems, 2021 AbstractOn the one hand, processors for hearing aids are highly specialized for audio processing, on the other hand they have to meet challenging hardware restrictions. This paper aims to provide an overview of the requirements, architectures, and implementations of these processors.
Lukas Gerlach 0001 +2 more
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Journal of Sensor and Actuator Networks, 2023 This work solves the problem of identification of the machine code architecture in cyberphysical devices. A basic systematization of the Executable and Linkable Format and Portable Executable formats of programs, as well as the analysis mechanisms used ...
Igor Kotenko +2 more
doaj +1 more source
Journal of Low Power Electronics and Applications, 2019 This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption.
Jennifer Hasler
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Digital implementation of the cellular sensor-computers [PDF]
, 2006 Two different kinds of cellular sensor-processor architectures are used nowadays in various applications. The first is the traditional sensor-processor architecture, where the sensor and the processor arrays are mapped into each other.
Benthien +36 more
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Implementing the conjugate gradient algorithm on multi-core systems [PDF]
, 2007 In linear solvers, like the conjugate gradient algorithm, sparse-matrix vector multiplication is an important kernel. Due to the sparseness of the matrices, the solver runs relatively slow.
Bakker, V. +3 more
core +4 more sources
A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs) [PDF]
IEEE Transactions on Biomedical Circuits and Systems, 2017 Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic ...
S. Moradi +3 more
semanticscholar +1 more source
Efficient FPSoC Prototyping of FCS-MPC for Three-Phase Voltage Source Inverters
Energies, 2020 This work describes an efficient implementation in terms of computation time and resource usage in a Field-Programmable System-On-Chip (FPSoC) of a Finite Control Set Model Predictive Control (FCS-MPC) algorithm. As an example, the FCS-MPC implementation
Eduardo Zafra +6 more
doaj +1 more source
Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review [PDF]
, 2009 The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range.
Gujarathi, Hemal S +2 more
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Digital Architectures for UWB Beamforming Using 2D IIR Spatio-Temporal Frequency-Planar Filters
International Journal of Antennas and Propagation, 2012 A design method and an FPGA-based prototype implementation of massively parallel systolic-array VLSI architectures for 2nd-order and 3rd-order frequency-planar beam plane-wave filters are proposed.
Soumya Kondapalli +2 more
doaj +1 more source