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The Architecture Of VLSI Digital Signal Processors
Twenty-Second Asilomar Conference on Signals, Systems and Computers, 2005With the introduction of now VLSI techniques, new levels of integration were possible. These new techniques and higher levels of integration allow the implementation of optimized processors for specific applications with large requirements. Real-Time Digital Signal Processing (RT-DSP) was an area whose requirements were riot achievable by the ...
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Session 2 overview: Processors: Digital architectures and systems subcommittee
2018 IEEE International Solid-State Circuits Conference - (ISSCC), 2018Continued growth in cloud-to-edge applications is driving innovations in digital processors. The first two papers of this session cover next-generation server-class processors. This is followed by an energy-efficient 14nm graphics processor. An SoC configurable with 1–4 chips on an MCM to service multiple markets is described next.
Thomas Burd +2 more
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Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040), 2003
The architectures of programmable digital signal processors have design constraints with different weights from general purpose microprocessors. The author considers how these differences have led to specializations of general purpose microprocessor architectural techniques.
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The architectures of programmable digital signal processors have design constraints with different weights from general purpose microprocessors. The author considers how these differences have led to specializations of general purpose microprocessor architectural techniques.
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IEEE Transactions on Acoustics, Speech, and Signal Processing, 1990
The authors present the design and evaluation of an architecture for a monolithic, programmable, floating-point digital signal processor (DSP) for instrumentation applications. An investigation of the most commonly used algorithms in instrumentation led to a design that satisfies the requirements for high computational and I/O (input/output) throughput.
Ronald D. Fellman +2 more
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The authors present the design and evaluation of an architecture for a monolithic, programmable, floating-point digital signal processor (DSP) for instrumentation applications. An investigation of the most commonly used algorithms in instrumentation led to a design that satisfies the requirements for high computational and I/O (input/output) throughput.
Ronald D. Fellman +2 more
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A Scalable and Programmable Simplicial CNN Digital Pixel Processor Architecture
IEEE Transactions on Circuits and Systems I: Regular Papers, 2004We propose a programmable architecture for a single instruction multiple data image processor that has its foundation on the mathematical framework of a simplicial cellular neural networks. We develop instruction primitives for basic image processing operations and show examples of processing binary and gray scale images.
Pablo Sergio Mandolesi +2 more
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A new processor architecture dedicated to digital modem applications
ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187), 2002The aim of this paper is to present a new processor architecture designed to cope with most of the functions of a high rate digital modem application. This work is part of an EURICO European project, whose target is the design of a TV cable modem. The paper introduces many of the aspects of the TV cable digital modem application.
F. Monteiro +3 more
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Digital Signal Processor: Architecture and Performance
Bell System Technical Journal, 1981This paper describes the DSP, a recently developed integrated circuit implementing a programmable digital signal processor. The single-chip device is fabricated in depletion-load NMOS and is packaged in a 40-pin DIP. It has the speed, precision, and flexibility for a variety of telecommunication applications.
J. R. Boddie +5 more
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Architectures for high performance digital control processors
IEE Colloquium on `Multiprocessor DSP (Digital Signal Processing) - Applications, Algorithms and Architectures', 1995This paper reports on a research project which is developing algorithms and architectures for a control system processor (CSP). The design considerations given suggest how new processor architectures targeted generally for critical linear time invariant systems can be arranged to yield higher performance controllers than those designed in the classical
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A digital signal processor module architecture and its implementation using VLSIs
ICASSP '84. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005A digital signal processor module (DSPM) has been developed for use in real-time processing of signals from acoustic arrays. This newly developed DSPM is characterized by flexibility; it is compact and gives high performance, and can be used in a wide range of applications.
K. Okada +5 more
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Architecture and applications of a 100-ns CMOS VLSI digital signal processor
ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005This paper describes the architecture and applications of a monolithic programmable CMOS VLSI Digital Signal Processor. The processor is based upon the architecture of its predecessor, TMS32020. The processor, which has 544 × 16 bit RAM and 4K × 16 ROM, executes instructions at a rate of 10 Million instructions per second.
S. Abiko +6 more
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