Results 311 to 320 of about 1,399,763 (373)

The architecture and applications of the motorola DSP56000 digital signal processor family

ICASSP '87. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005
This paper describes the architecture and applications of the DSP56001, a RAM-based member of the Motorola DSP56000 family of high performance, user-programmable CMOS digital signal processors. The DSP56001 has 512 × 24 bits of program RAM and special on-chip bootstrap hardware to download user programs from an external memory or host processor.
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Digital neural processor for parallel structure and cost performance comparison of the architectures

Proceedings of ICNN'95 - International Conference on Neural Networks, 2002
This paper introduces two processing elements, DNP (Digital Neural Processor)-I and DNP-II, which can be used to construct parallel structures for simulating large scale neural net(NN) models. The processors are designed with a digital VLSI, which consist of a minimum computation circuit for NN emulation including learning and a communication circuit ...
Jong-Moon Kim, Yoonseon Song, Myung-Won Kim   +2 more
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Optical Interconnection architectures for digital systems and processors

Annual Meeting Optical Society of America, 1986
We describe the use of bulk (3-D) optical systems in interconnection networks for electronic digital parallel processing and for telecommunications. More powerful computing architectures can be achieved through the use of parallel processors and the sharing of resources such as memory.
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Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014
Radio communication exhibits the highest energy consumption in wireless sensor nodes. Given their limited energy supply from batteries or scavenging, these nodes must trade data communication for on-the-node computation. Currently, they are designed around off-the-shelf low-power microcontrollers. But by employing a more appropriate processing element,
Cedric Walravens, Wim Dehaene
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Ultra-reliable digital avionics (URDA) processor architecture

Proceedings of National Aerospace and Electronics Conference (NAECON'94), 2002
The objective of the URDA program is to develop a prototype advanced development model (ADM) processor that combines a data processor, signal processor, memory and system interface on a single SEM-E avionics card. TI's approach integrates two Ada-programmable, URDA basic processor modules (BPMs) with a JIAWG-compatible PiBus and TMBus onto a common SEM-
R. Branstetter, A. Harper, L. Denton
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A Digital Processor Architecture for Combined EEG/EMG Falling Risk Prediction

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016
The brain signal anticipates the voluntary movement with patterns that can be detected even 500ms before the occurrence. This paper presents a digital signal processing unit which implements a real-time algorithm for falling risk prediction. The system architecture is designed to operate with digitized data samples from 8 EMG (limbs) and 8 EEG (motor ...
Valerio Francesco Annese, Marco Crepaldi, Danilo De Marchi, Daniela De Venuto   +3 more
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SPVA: A novel digital signal processor architecture for Software Defined Radio

2008 IEEE/ACS International Conference on Computer Systems and Applications, 2008
In this paper, we propose a new digital signal processor architecture SPVA (Scalable Parallel VLIW architecture) for Software Defined Radio. The proposed architecture organizes function units into arithmetic units, and other units. The former are organized as SIMD clusters and the latter are organized as control clusters.
Xing Fang, Dong Wang, Shuming Chen
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Nibble-serial: an architecture for VLSI digital signal processors

1988., IEEE International Symposium on Circuits and Systems, 2003
An architecture is proposed which can provide formidable processing power for the implementation of signal processing applications based on difference equations while still retaining the advantages of programmability. The architecture is based on a 4-bit-wide signal processing element (SPE), which is simple enough to be fabricated on a single VLSI ...
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Image Processors for Digital Angiography Algorithms and Architectures

1986
After a period of experimental and clinical development,(1–9) digital processing of angiographic X-ray video image sequences is now routinely applied in clinical and research work. The clinical advantages offered by this approach have been discussed in several reports.(10–12) The primary application is the improved visualization of regions of the heart
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Performance Study of Multicore Digital Signal Processor Architectures

The Journal of the Institute of Webcasting, Internet and Telecommunication, 2013
Due to the demand for high speed 3D graphic rendering, video file format conversion, compression, encryption and decryption technologies, the importance of digital signal processor system is growing rapidly. In order to satisfy the real-time constraints, high performance digital signal processor is required.
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