Results 321 to 330 of about 1,399,763 (373)

An asynchronous architecture for digital signal processors

Proceedings European Design and Test Conference. ED & TC 97, 1997
M. R. Karthikeyan, Soumitra Kumar Nandy
openaire   +1 more source

Architectural analysis of a shared resource digital signal processor

Proceedings of the IEEE 1988 National Aerospace and Electronics Conference, 2003
The processor-simulation approach taken for the Westinghouse signal processor architectural simulator is described. Detailed representations of the Westinghouse distributed operating system and abstract representations of the physical capabilities of the hardware provide a shell for the analysis of signal processing activity.
openaire   +1 more source

Single-chip image sensors with a digital processor array

J. VLSI Signal Process., 1993
R. Forchheimer, Keping Chen, C. Svensson, A. Ödmark   +3 more
semanticscholar   +1 more source

Low Latency Recovery from Transient Faults for Pipelined Processor Architectures

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010
M. Jeitler, Jakob Lechner
semanticscholar   +1 more source

Design issues and an architecture for the monolithic implementation of a parallel digital signal processor

IEEE Transactions on Acoustics, Speech, and Signal Processing, 1990
Design issues in the implementation of a parallel digital signal processor for measurement systems are discussed. Constraints imposed by the application and VLSI technology are shown to lead to the design criteria of modularity, flexibility, programmability, and high speed.
openaire   +1 more source

The Evolution to Modern Phased Array Architectures

Proceedings of the IEEE, 2016
J. Herd, M. Conway
semanticscholar   +1 more source

Architectures of flexible symmetric key crypto engines—a survey: From hardware coprocessor to multi-crypto-processor system on chip

CSUR, 2013
L. Bossuet, M. Grand, Lubos Gaspar, V. Fischer, G. Gogniat   +4 more
semanticscholar   +1 more source

Targeted Processor Architectures for High-Performance Controller Implementation

, 1997
Simon Jones, R. Goodall, M. Gooch
semanticscholar   +1 more source

Parallel processor architecture for a digital beacon receiver

2014
A digital beacon receiver has been developed to monitor the OLYMPUS satellite beacons. The receiver accepts a nominal 10 MHz IF input and processes the signal using digital signal processing techniques. Fast Fourier transforms are used to locate the carrier within 0.5 Hz. The outputs of the receiver include the frequency and the power of the carrier.
openaire   +1 more source

Feasibility analysis of baseband architectures for multi-GNSS receivers

GPS Solutions, 2016
V. Tran, N. Shivaramaiah, A. Dempster
semanticscholar   +1 more source