Results 201 to 210 of about 94,953 (264)

Research and Implement of Digital Receiver

2010 International Conference on Signal Acquisition and Processing, 2010
In order to detect weak signal in complex background, the paper studies and realizes six-channel digital receiver. Receiver is designed as much digital structure as possible, the basic hardware parameters of receiver can be adjust to meet different needs of specific applications by calling the corresponding software packages.
Dingkun Ma, Xiaomin Zhang, Jian Luo
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Realization of digital coherent receivers

2009 IEEE LEOS Annual Meeting Conference Proceedings, 2009
The hardware architecture of digital coherent optical receivers supporting ≫40 Gb/s data rates and general considerations about signal processing algorithms are presented as well as a chipset layout for a 40 Gb/s digital coherent polarization-multiplexed QPSK receiver.
Noe, Reinhold, Rückert, Ulrich, Hoffmann, Sebastian, Pfau, Timo, Peveling, Ralf, ARRAY(0x26da1098)   +5 more
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Digital TV receiver with a low IF

IEEE Transactions on Consumer Electronics, 1993
A TV receiver design that uses the quadrature-receiver principle is presented. Due to a low IF (intermediate frequency) of 2.6 MHz, normal video analog-to-digital (A/D) converters are sufficient to digitize the complete modulated signal. A lot of RF processing is done within the digital domain.
D. Ehrhardt, T. Benkner
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A digital multistandard paging receiver

IEEE Transactions on Consumer Electronics, 1999
Many different paging systems exist. Therefore it is very desirable to be able to implement the paging receiver in a way that all major paging standards can be supported. In this paper, a software radio receiver architecture which uses a signal demodulation technique based on a complex digital phase-locked loop is presented. This kind of software radio
openaire   +1 more source