Results 231 to 240 of about 88,416 (262)

A floating-point digital receiver for MRI

IEEE Transactions on Biomedical Engineering, 2002
A magnetic resonance imaging (MRI) system requires the highest possible signal fidelity and stability for clinical applications. Quadrature analog receivers have problems with channel matching, dc offset and analog-to-digital linearity. Fixed-point digital receivers (DRs) reduce all of these problems. We have demonstrated that a floating-point DR using
John C. Hoenninger III, Lawrence E. Crooks, Mitsuaki Arakawa   +2 more
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Low-power digital CDMA receiver

Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, 2003
The advanced design tasks for a digital CDMA receiver are presented in this report. A biased number system and architecture are used to reduce the switching activity to reduce power consumption. A carry-save adder tree is used to speed up the summation of 127 data (3 bits) in the synchronization and date extraction process.
Ja-Sheng Liu, I-Hsin Chen, Yi-Chen Tsai, Shyh-Jye Jou   +3 more
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A digital receiver architecture for RFID readers

2008 International Symposium on Industrial Embedded Systems, 2008
This paper presents a digital receiver architecture for an RFID reader. The main challenge in RFID reader design is the detection of the backscattered signals from the tags, which can be severely complicated due to the largely varying scale of possible receive powers.
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Channelized digital receivers for impulse radio

IEEE International Conference on Communications, 2003. ICC '03., 2004
Critical to the design of a digital impulse radio (IR) receiver is the ability of the analog-to-digital converter (ADC) to efficiently sample and digitize the received signal at the signal Nyquist rate of several gigahertz. Since designing a single ADC to operate at such frequencies is not practical, channelized receivers that efficiently sample at a ...
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Timing Recovery in Digital Synchronous Data Receivers

IEEE Transactions on Communications, 1976
A new class of fast-converging timing recovery methods for synchronous digital data receivers is investigated. Starting with a worst-case timing offset, convergence with random binary data will typically occur within 10-20 symbols. The input signal is sampled at the baud rate; these samples are then processed to derive a suitable control signal to ...
Kurt H. Mueller, Markus Müller
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Digital Receiver Phase Meter for LISA

IEEE Transactions on Instrumentation and Measurement, 2005
A study of a commercially available digital receiver configured as a phase meter has been performed. The effort was part of the technology development phase of the Laser Interferometer Space Antenna (LISA) mission. LISA requires that phase measurements on the metrology signals be made at a rate of 10 Hz with root power spectral density of 5 /spl mu ...
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DIGITAL INFORMATION RECEIVER BASED ON STOCHASTIC RESONANCE

International Journal of Bifurcation and Chaos, 2003
An electronic receiver based on stochastic resonance is presented to rescue subthreshold modulated digital data. In real experiment, it is shown that a complete data restoration is achieved for both uniform and Gaussian white noise.
Morfu, Saverio, Bilbault, Jean-Marie, Comte, Jean-Christophe   +2 more
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Digitalization of receivables management

2019
© 2019, Research Trend. All rights reserved. This article describes the ability to manage the company's receivables using modern software products. We carried out the research of receivables and its place in the structure of the company's assets. The main target of receivables management is determined as optimizing of its level but not reducing.
Bikchantaeva D., Samolyanov P., Stepanova I.   +2 more
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Design and Performance of a Digital Multifrequency Receiver

IEEE Transactions on Communications, 1977
An experimental multifrequency receiver for recognition of digitally encoded multifrequency signaling was designed, constructed and tested. The receiver is based on a quadrature detection technique that consists of digital demodulation followed by second-order, lowpass digital filtering.
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Analog-to-Digital Converter Selection for Digital Receiver

2019 Systems of Signal Synchronization, Generating and Processing in Telecommunications (SYNCHROINFO), 2019
There are computational and empirical approaches to analog-to-digital converter (ADC) selection in digital receiver. Simplified calculation methods are based on the idealized ADC model. These methods take into account only the quantization noise associated with the ADC bits number, sampling frequency, signal-to-noise ratio.
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