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Fast Digitization and Digital Receiver Technology
AIP Conference Proceedings, 2002The potentially lucrative wireless market has led to technological advances in mixed signal devices such as high speed, high resolution A/D and D/A converters. This same market has also driven the development of high performance multi‐channel digital receiver and digital transmitter ICs.
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6th International Conference on Radio Receivers and Associated Systems, 1995
The paper describes an experimental digital receiver (tuner) for wideband applications in the HF-band. The output from the receiver is an undemodulated digitised signal with 750 kHz of useful bandwidth. The 5 MHz sampling frequency is generous compared to the bandwidth. This relaxes the demands on the analogue components and gives us the possibility of
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The paper describes an experimental digital receiver (tuner) for wideband applications in the HF-band. The output from the receiver is an undemodulated digitised signal with 750 kHz of useful bandwidth. The 5 MHz sampling frequency is generous compared to the bandwidth. This relaxes the demands on the analogue components and gives us the possibility of
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A Digital Receiver for Tone Detection Applications
IEEE Transactions on Communications, 1976A digital circuit suitable for detection of tones in signaling applications is described. The amount of hardware required for the realization of the circuit is shown to be quite small. The circuit may be used for both analog and digital input signals. For analog signals, the necessary A/D conversion becomes very simple.
Theo A. C. M. Claasen, J. B. H. Peek
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A floating-point digital receiver for MRI
IEEE Transactions on Biomedical Engineering, 2002A magnetic resonance imaging (MRI) system requires the highest possible signal fidelity and stability for clinical applications. Quadrature analog receivers have problems with channel matching, dc offset and analog-to-digital linearity. Fixed-point digital receivers (DRs) reduce all of these problems. We have demonstrated that a floating-point DR using
John C. Hoenninger III +2 more
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A digital receiver architecture for RFID readers
2008 International Symposium on Industrial Embedded Systems, 2008This paper presents a digital receiver architecture for an RFID reader. The main challenge in RFID reader design is the detection of the backscattered signals from the tags, which can be severely complicated due to the largely varying scale of possible receive powers.
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IEEE Transactions on Aerospace and Electronic Systems, 1966
Digital computers have evolved to an active role as components in communication systems, performing such functions as data processing, executive and adaptive control, management of waveform, and antenna characteristic selection. At one time, the interface between communication equipment and data processing was clear.
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Digital computers have evolved to an active role as components in communication systems, performing such functions as data processing, executive and adaptive control, management of waveform, and antenna characteristic selection. At one time, the interface between communication equipment and data processing was clear.
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Channelized digital receivers for impulse radio
IEEE International Conference on Communications, 2003. ICC '03., 2004Critical to the design of a digital impulse radio (IR) receiver is the ability of the analog-to-digital converter (ADC) to efficiently sample and digitize the received signal at the signal Nyquist rate of several gigahertz. Since designing a single ADC to operate at such frequencies is not practical, channelized receivers that efficiently sample at a ...
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Low-power digital CDMA receiver
Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, 2003The advanced design tasks for a digital CDMA receiver are presented in this report. A biased number system and architecture are used to reduce the switching activity to reduce power consumption. A carry-save adder tree is used to speed up the summation of 127 data (3 bits) in the synchronization and date extraction process.
Ja-Sheng Liu +3 more
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Timing Recovery in Digital Synchronous Data Receivers
IEEE Transactions on Communications, 1976A new class of fast-converging timing recovery methods for synchronous digital data receivers is investigated. Starting with a worst-case timing offset, convergence with random binary data will typically occur within 10-20 symbols. The input signal is sampled at the baud rate; these samples are then processed to derive a suitable control signal to ...
Kurt H. Mueller, Markus Müller
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Digital Receiver Phase Meter for LISA
IEEE Transactions on Instrumentation and Measurement, 2005A study of a commercially available digital receiver configured as a phase meter has been performed. The effort was part of the technology development phase of the Laser Interferometer Space Antenna (LISA) mission. LISA requires that phase measurements on the metrology signals be made at a rate of 10 Hz with root power spectral density of 5 /spl mu ...
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