Results 211 to 220 of about 55,221 (243)

Floating Point Complex Multiplier Using Urdhva-Tiryakbhyam Sutra

International Conference on Cryptography, Security and Privacy
Using the Vedic Urdhva - Tiryakbhyam Sutra(VUTS), Rao et al. proposed a model for a complex number multiplier. It is unable to employ floating-point numbers for complex arithmetic using this vedic method, because their model is only made for whole ...
H. R, Shyamsundhar S, Dhuwarakesh V, Vaidehi Vijayakumar   +3 more
semanticscholar   +1 more source

Correct Rounding in Double Extended Precision

IEEE Symposium on Computer Arithmetic
The double extended precision format is an 80-bit floating-point format introduced in the 80x87 series of floating-point processors by Intel. Since the introduction of vector instructions in the x86 processors, its use has fallen due to speed concerns ...
Sélène Corbineau, Paul Zimmermann
semanticscholar   +1 more source

IEEE 754-Based Single- and Double-Precision Floating-Point Multiplier Analysis

Advances in Intelligent Systems and Computing, 2019
S. A. Shaikh, B. Godbole, U. Shiurkar
semanticscholar   +1 more source

An asynchronous double precision floating point multiplier

IEEE International Conference on Electrical, Computer and Communication Technologies, 2015
S. Nair, Sudarshan TSB
semanticscholar   +1 more source

An FPGA based high speed IEEE-754 double precision floating point multiplier using Verilog

2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), 2013
A. P. Ramesh, A. Tilak, A. M. Prasad
semanticscholar   +1 more source

OME-NGFF: a next-generation file format for expanding bioimaging data-access strategies

Nature Methods, 2021
Josh Moore, Sébastien Besson, Erin Diel
exaly  

A PRNG Specialized in Double Precision Floating Point Numbers Using an Affine Transition

, 2009
Mutsuo Saito, M. Matsumoto
semanticscholar   +1 more source

An Implementation of Double precision Floating point Adder & Subtractor Using Verilog

, 2014
Sonali M. Rane, T. Wagh, P. Malathi
semanticscholar   +1 more source

Implementing Sticky Bit Generators Based on FPGA Carry-Chains for Floating-Point Adders

Computer Science On-line Conference, 2020
I. V. Ushenina, E. Chirkova
semanticscholar   +1 more source

LDBlockShow: a fast and convenient tool for visualizing linkage disequilibrium and haplotype blocks based on variant call format files

Briefings in Bioinformatics, 2021
Shan-Shan Dong, Wei-Ming He, Yan Guo
exaly